Kyle Roarty has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/48019 )
Change subject: arch-gcn3: Free dest registers in non-memory Load DS insts
......................................................................
arch-gcn3: Free dest registers in non-memory Load DS insts
Certain DS insts are classfied as Loads, but don't actually go through
the memory pipeline. However, any instruction classified as a load
marks its destination registers as free in the memory pipeline.
Because these instructions didn't use the memory pipeline, they
never freed their destination registers, which led to a deadlock.
This patch explicitly calls the function used to free the destination
registers in the execute() method of those Load instructions that
don't use the memory pipeline.
Change-Id: Ic2ac2e232c8fbad63d0c62c1862f2bdaeaba4edf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48019
Reviewed-by: Matt Sinclair <mattdsincl...@gmail.com>
Reviewed-by: Bobby R. Bruce <bbr...@ucdavis.edu>
Maintainer: Matt Sinclair <mattdsincl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/amdgpu/gcn3/insts/instructions.cc
1 file changed, 27 insertions(+), 0 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, but someone else must approve; Looks
good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/gcn3/insts/instructions.cc
b/src/arch/amdgpu/gcn3/insts/instructions.cc
index a421454..21ab58d 100644
--- a/src/arch/amdgpu/gcn3/insts/instructions.cc
+++ b/src/arch/amdgpu/gcn3/insts/instructions.cc
@@ -32397,6 +32397,15 @@
}
vdst.write();
+
+ /**
+ * This is needed because we treat this instruction as a load
+ * but it's not an actual memory request.
+ * Without this, the destination register never gets marked as
+ * free, leading to a possible deadlock
+ */
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
} // execute
// --- Inst_DS__DS_PERMUTE_B32 class methods ---
@@ -32468,6 +32477,15 @@
wf->decLGKMInstsIssued();
wf->rdLmReqsInPipe--;
wf->validateRequestCounters();
+
+ /**
+ * This is needed because we treat this instruction as a load
+ * but it's not an actual memory request.
+ * Without this, the destination register never gets marked as
+ * free, leading to a possible deadlock
+ */
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
} // execute
// --- Inst_DS__DS_BPERMUTE_B32 class methods ---
@@ -32539,6 +32557,15 @@
wf->decLGKMInstsIssued();
wf->rdLmReqsInPipe--;
wf->validateRequestCounters();
+
+ /**
+ * This is needed because we treat this instruction as a load
+ * but it's not an actual memory request.
+ * Without this, the destination register never gets marked as
+ * free, leading to a possible deadlock
+ */
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
} // execute
// --- Inst_DS__DS_ADD_U64 class methods ---
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-1
Gerrit-Change-Id: Ic2ac2e232c8fbad63d0c62c1862f2bdaeaba4edf
Gerrit-Change-Number: 48019
Gerrit-PatchSet: 2
Gerrit-Owner: Kyle Roarty <kyleroarty1...@gmail.com>
Gerrit-Reviewer: Alex Dutu <alexandru.d...@amd.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Kyle Roarty <kyleroarty1...@gmail.com>
Gerrit-Reviewer: Matt Sinclair <mattdsincl...@gmail.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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