Daecheol You has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48403 )
Change subject: mem-ruby: Atomic transaction support for CHI protocol
......................................................................
mem-ruby: Atomic transaction support for CHI protocol
Ruby assumes protocols use directory controllers as memory interface.
Thus, recvAtomic() uses the machine type of directory when it calls
mapAddressToMachine(). However, it doesn't work for CHI since
CHI does not use directory controllers as memory controller interface.
Therefore, the code was modified to check which controller type is used
for memory interface between MachineType_Directory and
MachineType_Memory, which is used for CHI.
Change-Id: If35a06a8a3772ce5e5b994df05c9d94c7770c90d
---
M src/mem/ruby/system/RubyPort.cc
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index e2266b6..7127862 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -345,16 +345,24 @@
RubySystem::getBlockSizeBytes());
}
- // Find appropriate directory for address
- // This assumes that protocols have a Directory machine,
- // which has its memPort hooked up to memory. This can
- // fail for some custom protocols.
- MachineID id = ruby_port->m_controller->mapAddressToMachine(
- pkt->getAddr(), MachineType_Directory);
+ // Find the machine type of memory controller interface
RubySystem *rs = ruby_port->m_ruby_system;
- AbstractController *directory =
- rs->m_abstract_controls[id.getType()][id.getNum()];
- Tick latency = directory->recvAtomic(pkt);
+ static int mem_interface_type = -1;
+ if (mem_interface_type == -1) {
+ if (rs->m_abstract_controls[MachineType_Directory].size() != 0)
+ mem_interface_type = MachineType_Directory;
+ else if (rs->m_abstract_controls[MachineType_Memory].size() != 0)
+ mem_interface_type = MachineType_Memory;
+ else
+ fatal("The protocol has no memory controller interface");
+ }
+
+ // Find the controller for the target address
+ MachineID id = ruby_port->m_controller->mapAddressToMachine(
+ pkt->getAddr(), (MachineType)mem_interface_type);
+ AbstractController *mem_interface =
+ rs->m_abstract_controls[mem_interface_type][id.getNum()];
+ Tick latency = mem_interface->recvAtomic(pkt);
if (access_backing_store)
rs->getPhysMem()->access(pkt);
return latency;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48403
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If35a06a8a3772ce5e5b994df05c9d94c7770c90d
Gerrit-Change-Number: 48403
Gerrit-PatchSet: 1
Gerrit-Owner: Daecheol You <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
