Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48706 )
Change subject: cpu: Add a mechanism which lets a reg class name its
members.
......................................................................
cpu: Add a mechanism which lets a reg class name its members.
This can be used to get the "pretty" name for a given register index
within a register class, and can be specialized per ISA, or even per ISA
object.
Change-Id: I7b290db73c7d04e0f61293ae82fc92ca5b4fe692
---
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/src/cpu/reg_class.cc b/src/cpu/reg_class.cc
index c806560..fc39e42 100644
--- a/src/cpu/reg_class.cc
+++ b/src/cpu/reg_class.cc
@@ -39,10 +39,17 @@
*/
#include "cpu/reg_class.hh"
+#include "base/cprintf.hh"
namespace gem5
{
+std::string
+DefaultRegClassOps::regName(const RegId &id) const
+{
+ return csprintf("r%d", id.index());
+}
+
const char *RegId::regClassStrings[] = {
"IntRegClass",
"FloatRegClass",
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index eaa2c0e..0b57487 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -43,6 +43,7 @@
#include <cassert>
#include <cstddef>
+#include <string>
#include "arch/vecregs.hh"
#include "base/types.hh"
@@ -65,19 +66,43 @@
MiscRegClass ///< Control (misc) register
};
+class RegId;
+
+class RegClassOps
+{
+ public:
+ virtual std::string regName(const RegId &id) const = 0;
+};
+
+class DefaultRegClassOps : public RegClassOps
+{
+ public:
+ std::string regName(const RegId &id) const override;
+};
+
class RegClassInfo
{
private:
size_t _size;
const RegIndex _zeroReg;
+ static inline DefaultRegClassOps defaultOps;
+ RegClassOps *_ops = &defaultOps;
+
public:
- RegClassInfo(size_t new_size, RegIndex new_zero = -1) :
+ RegClassInfo(size_t new_size, RegIndex new_zero=-1) :
_size(new_size), _zeroReg(new_zero)
{}
+ RegClassInfo(size_t new_size, RegClassOps &new_ops, RegIndex
new_zero=-1) :
+ RegClassInfo(new_size, new_zero)
+ {
+ _ops = &new_ops;
+ }
size_t size() const { return _size; }
RegIndex zeroReg() const { return _zeroReg; }
+
+ std::string regName(const RegId &id) const { return _ops->regName(id);
}
};
/** Register ID: describe an architectural register with its class and
index.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7b290db73c7d04e0f61293ae82fc92ca5b4fe692
Gerrit-Change-Number: 48706
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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