[gem5-dev] Change in gem5/gem5[develop]: arm: Make the misc reg class return the name of misc regs.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48707 )

Change subject: arm: Make the misc reg class return the name of misc regs.
......................................................................

arm: Make the misc reg class return the name of misc regs.

Change-Id: Ic2c8576b079c68f28b48006dd90515b1a5c68ed9
---
M src/arch/arm/isa.cc
1 file changed, 12 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index cb3d4ec..51856ca 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -45,6 +45,7 @@
 #include "arch/arm/self_debug.hh"
 #include "arch/arm/system.hh"
 #include "arch/arm/tlbi_op.hh"
+#include "base/cprintf.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/reg_class.hh"
@@ -64,6 +65,16 @@
 namespace ArmISA
 {

+class MiscRegClassOps : public RegClassOps
+{
+  public:
+    std::string
+    regName(const RegId &id) const override
+    {
+        return miscRegName[id.index()];
+    }
+} miscRegClassOps;
+
 ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
     _decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
     afterStartup(false)
@@ -74,7 +85,7 @@
     _regClasses.emplace_back(NumVecRegs * TheISA::NumVecElemPerVecReg);
     _regClasses.emplace_back(NumVecPredRegs);
     _regClasses.emplace_back(NUM_CCREGS);
-    _regClasses.emplace_back(NUM_MISCREGS);
+    _regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps);

     miscRegs[MISCREG_SCTLR_RST] = 0;


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic2c8576b079c68f28b48006dd90515b1a5c68ed9
Gerrit-Change-Number: 48707
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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