Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48713 )
Change subject: arm: Use operands and not an ExecContext accessor for misc
regs.
......................................................................
arm: Use operands and not an ExecContext accessor for misc regs.
The operands an instruction accesses should be known to the ISA parser
so that it has a chance to manage them, and CPU models have a chance to
interact with them intelligently. The readMiscReg and setMiscReg methods
on the ExecContext interface defeat that by only letting anybody else
know what operands they want at execution time instead of decode time.
The one exception to this is current in arch/arm/isa/insts/misc.isa,
where the index for misc registers is determined by a complex decoding
function. This code can be and should be refactored so that this
accessor will become unnecessary there as well. That will involve
separating the part that checks whether a register is accessible in the
current circumstances and the part that decodes an index, and also
pulling out the logic which determines integer vs misc register so those
can be implemented as two different instructions.
Change-Id: I7ec7bdbcdcb65cc8b62681a038f75f0cd530b2c0
---
M src/arch/arm/isa/insts/branch64.isa
M src/arch/arm/isa/insts/crypto.isa
M src/arch/arm/isa/insts/crypto64.isa
M src/arch/arm/isa/insts/neon.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/operands.isa
6 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/src/arch/arm/isa/insts/branch64.isa
b/src/arch/arm/isa/insts/branch64.isa
index 10a352f..ebe66a6 100644
--- a/src/arch/arm/isa/insts/branch64.isa
+++ b/src/arch/arm/isa/insts/branch64.isa
@@ -207,13 +207,13 @@
ExceptionLevel curr_el = currEL(cpsr);
switch (curr_el) {
case EL3:
- newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL3);
+ newPc = ElrEl3;
break;
case EL2:
- newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL2);
+ newPc = ElrEl2;
break;
case EL1:
- newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL1);
+ newPc = ElrEl1;
break;
default:
return std::make_shared<UndefinedInstruction>(machInst,
diff --git a/src/arch/arm/isa/insts/crypto.isa
b/src/arch/arm/isa/insts/crypto.isa
index b6c3ad3..6ce83ca 100644
--- a/src/arch/arm/isa/insts/crypto.isa
+++ b/src/arch/arm/isa/insts/crypto.isa
@@ -38,8 +38,7 @@
let {{
cryptoEnabledCheckCode = '''
- auto crypto_reg = xc->tcBase()->readMiscReg(MISCREG_ID_ISAR5);
- if (!(crypto_reg & %(mask)d)) {
+ if (!(Isar5 & %(mask)d)) {
return std::make_shared<UndefinedInstruction>(machInst, true);
}
'''
diff --git a/src/arch/arm/isa/insts/crypto64.isa
b/src/arch/arm/isa/insts/crypto64.isa
index 35ea4fe..3ec68e8 100644
--- a/src/arch/arm/isa/insts/crypto64.isa
+++ b/src/arch/arm/isa/insts/crypto64.isa
@@ -41,8 +41,7 @@
exec_output = ""
cryptoEnabledCheckCode = '''
- auto crypto_reg =
xc->tcBase()->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
- if (!(crypto_reg & %(mask)d)) {
+ if (!(Aa64isar0El1 & %(mask)d)) {
return std::make_shared<UndefinedInstruction>(machInst, true);
}
'''
diff --git a/src/arch/arm/isa/insts/neon.isa
b/src/arch/arm/isa/insts/neon.isa
index 756abdc..e7ecfeb 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -2813,8 +2813,7 @@
vqrdmlahCode = vqrdmCode % {'code': code_add}
rdm_check = '''
int sz = bits(machInst, 21, 20);
- RegVal isar5 = xc->tcBase()->readMiscReg(MISCREG_ID_ISAR5);
- if (!(bits(isar5, 27, 24) == 0x1) || sz == 3 || sz == 0)
+ if (!(bits(Isar5, 27, 24) == 0x1) || sz == 3 || sz == 0)
return std::make_shared<UndefinedInstruction>(machInst, true);
typedef __int128_t BigElement;
'''
diff --git a/src/arch/arm/isa/insts/neon64.isa
b/src/arch/arm/isa/insts/neon64.isa
index d867907..6b9c8cc 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -2354,7 +2354,7 @@
sqrdmlahCode = sqrdmCode % {'code': code_add}
rdm_check = '''
int sz = bits(machInst, 23, 22);
- AA64ISAR0 isar0 = xc->tcBase()->readMiscReg(
MISCREG_ID_AA64ISAR0_EL1);
+ AA64ISAR0 isar0 = Aa64isar0El1;
if (!isar0.rdm || sz == 3 || sz == 0)
return std::make_shared<UndefinedInstruction>(machInst, true);
typedef __int128_t BigElement;
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 82e7466..21eac7f 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -410,6 +410,7 @@
'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),
#Fixed index control regs
+ 'Aa64isar0El1': cntrlReg('MISCREG_ID_AA64ISAR0_EL1'),
'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
'Spsr': cntrlRegNC('MISCREG_SPSR'),
@@ -422,11 +423,15 @@
'Cpacr64': cntrlReg('MISCREG_CPACR_EL1'),
'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
'Nsacr': cntrlReg('MISCREG_NSACR'),
+ 'ElrEl1': cntrlRegNC('MISCREG_ELR_EL1'),
+ 'ElrEl2': cntrlRegNC('MISCREG_ELR_EL2'),
+ 'ElrEl3': cntrlRegNC('MISCREG_ELR_EL3'),
'ElrHyp': cntrlRegNC('MISCREG_ELR_HYP'),
'Hcr': cntrlReg('MISCREG_HCR'),
'Hcr64': cntrlReg('MISCREG_HCR_EL2'),
'Hdcr': cntrlReg('MISCREG_HDCR'),
'Hcptr': cntrlReg('MISCREG_HCPTR'),
+ 'Isar5': cntrlReg('MISCREG_ID_ISAR5'),
'CptrEl264': cntrlReg('MISCREG_CPTR_EL2'),
'CptrEl364': cntrlReg('MISCREG_CPTR_EL3'),
'Hstr': cntrlReg('MISCREG_HSTR'),
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48713
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7ec7bdbcdcb65cc8b62681a038f75f0cd530b2c0
Gerrit-Change-Number: 48713
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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