Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49084 )
Change subject: arch-arm: Replace std::tie with C++17 structured binding
......................................................................
arch-arm: Replace std::tie with C++17 structured binding
Change-Id: I856b60e91a0c8089ccc3560bdf9024b42206e170
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/utility.cc
3 files changed, 19 insertions(+), 29 deletions(-)
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index 2b00a77..d6ca535 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1129,8 +1129,7 @@
return true;
bool spsr_mode_is_aarch32 = (spsr.width == 1);
- bool known, target_el_is_aarch32;
- std::tie(known, target_el_is_aarch32) = ELUsingAArch32K(tc, target_el);
+ auto [known, target_el_is_aarch32] = ELUsingAArch32K(tc, target_el);
assert(known || (target_el == EL0 && ELIs64(tc, EL1)));
if (known && (spsr_mode_is_aarch32 != target_el_is_aarch32))
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index 176e031..a773749 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -891,9 +891,8 @@
mrc14code = '''
MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
RegId(MiscRegClass, op1)).index();
- bool can_read, undefined;
- std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr,
- xc->tcBase());
+ auto [can_read, undefined] = canReadCoprocReg(miscReg, Scr, Cpsr,
+ xc->tcBase());
if (!can_read || undefined) {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
@@ -917,9 +916,8 @@
mcr14code = '''
MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
RegId(MiscRegClass, dest)).index();
- bool can_write, undefined;
- std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr,
- xc->tcBase());
+ auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
+ xc->tcBase());
if (undefined || !can_write) {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
@@ -947,9 +945,8 @@
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
- bool can_read, undefined;
- std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr,
- xc->tcBase());
+ auto [can_read, undefined] = canReadCoprocReg(miscReg, Scr, Cpsr,
+ xc->tcBase());
// if we're in non secure PL1 mode then we can trap regargless of
whether
// the register is accessable, in other modes we trap if only if the
register
// IS accessable.
@@ -980,9 +977,8 @@
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
- bool can_write, undefined;
- std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr,
- xc->tcBase());
+ auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
+ xc->tcBase());
// if we're in non secure PL1 mode then we can trap regargless of
whether
// the register is accessable, in other modes we trap if only if the
register
@@ -1014,9 +1010,8 @@
Fault fault = mcrrMrrc15Trap(miscReg, machInst, xc->tcBase(), imm);
- bool can_read, undefined;
- std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr,
- xc->tcBase());
+ auto [can_read, undefined] = canReadCoprocReg(miscReg, Scr, Cpsr,
+ xc->tcBase());
// if we're in non secure PL1 mode then we can trap regargless of
whether
// the register is accessable, in other modes we trap if only if the
register
// IS accessable.
@@ -1047,9 +1042,8 @@
Fault fault = mcrrMrrc15Trap(miscReg, machInst, xc->tcBase(), imm);
- bool can_write, undefined;
- std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr,
- xc->tcBase());
+ auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
+ xc->tcBase());
// if we're in non secure PL1 mode then we can trap regargless of
whether
// the register is accessable, in other modes we trap if only if the
register
@@ -1125,9 +1119,8 @@
bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
- bool can_write, undefined;
- std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr,
Cpsr,
- xc->tcBase());
+ auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
+ xc->tcBase());
// if we're in non secure PL1 mode then we can trap regardless
// of whether the register is accessible, in other modes we
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 4c1acb5..bd1af44 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -287,8 +287,7 @@
bool
ELIs32(ThreadContext *tc, ExceptionLevel el)
{
- bool known, aarch32;
- std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
+ auto [known, aarch32] = ELUsingAArch32K(tc, el);
panic_if(!known, "EL state is UNKNOWN");
return aarch32;
}
@@ -375,11 +374,10 @@
return std::make_pair(known, aarch32);
}
-bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
+bool
+ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
{
-
- bool known, aarch32;
- std::tie(known, aarch32) = ELStateUsingAArch32K(tc, el, secure);
+ auto [known, aarch32] = ELStateUsingAArch32K(tc, el, secure);
panic_if(!known, "EL state is UNKNOWN");
return aarch32;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I856b60e91a0c8089ccc3560bdf9024b42206e170
Gerrit-Change-Number: 49084
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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