Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/48965 )
Change subject: scons: Turn the ISA and GPU ISA lists into construction
variables.
......................................................................
scons: Turn the ISA and GPU ISA lists into construction variables.
Change-Id: I4135709f5bceee959b5178a4700656aa782b1d6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48965
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
Reviewed-by: Bobby R. Bruce <[email protected]>
---
M src/SConscript
M src/arch/SConsopts
M src/arch/amdgpu/gcn3/SConsopts
M src/arch/amdgpu/vega/SConsopts
M src/arch/arm/SConsopts
M src/arch/mips/SConsopts
M src/arch/null/SConsopts
M src/arch/power/SConsopts
M src/arch/riscv/SConsopts
M src/arch/sparc/SConsopts
M src/arch/x86/SConsopts
M src/cpu/SConsopts
M src/cpu/checker/SConsopts
M src/cpu/minor/SConsopts
M src/cpu/o3/SConsopts
M src/cpu/simple/SConsopts
16 files changed, 21 insertions(+), 33 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/SConscript b/src/SConscript
index 7ea946b..bc19ac9 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -709,7 +709,7 @@
env.ConfigFile(opt)
def makeTheISA(source, target, env):
- isas = [ src.get_contents().decode('utf-8') for src in source ]
+ isas = sorted(set(env.Split('${ALL_ISAS}')))
target_isa = env['TARGET_ISA']
is_null_isa = '1' if (target_isa.lower() == 'null') else '0'
@@ -740,11 +740,11 @@
code.write(str(target[0]))
-env.Command('config/the_isa.hh', list(map(Value, all_isa_list)),
+env.Command('config/the_isa.hh', [],
MakeAction(makeTheISA, Transform("CFG ISA", 0)))
def makeTheGPUISA(source, target, env):
- isas = [ src.get_contents().decode('utf-8') for src in source ]
+ isas = sorted(set(env.Split('${ALL_ISAS}')))
target_gpu_isa = env['TARGET_GPU_ISA']
def define(isa):
return str(isa.upper()) + '_ISA'
@@ -782,7 +782,7 @@
code.write(str(target[0]))
-env.Command('config/the_gpu_isa.hh', list(map(Value, all_gpu_isa_list)),
+env.Command('config/the_gpu_isa.hh', [],
MakeAction(makeTheGPUISA, Transform("CFG ISA", 0)))
########################################################################
diff --git a/src/arch/SConsopts b/src/arch/SConsopts
index 90ac93b..38b02f5 100644
--- a/src/arch/SConsopts
+++ b/src/arch/SConsopts
@@ -25,18 +25,12 @@
Import('*')
-# Define the universe of supported ISAs
-all_isa_list = []
-Export('all_isa_list')
-
-all_gpu_isa_list = []
-Export('all_gpu_isa_list')
-
def add_isa_lists():
sticky_vars.AddVariables(
- EnumVariable('TARGET_ISA', 'Target ISA', 'null',
sorted(all_isa_list)),
+ EnumVariable('TARGET_ISA', 'Target ISA', 'null',
+ sorted(set(main.Split('${ALL_ISAS}')))),
EnumVariable('TARGET_GPU_ISA', 'Target GPU ISA', 'gcn3',
- sorted(all_gpu_isa_list)),
+ sorted(set(main.Split('${ALL_GPU_ISAS}')))),
)
AfterSConsopts(add_isa_lists)
diff --git a/src/arch/amdgpu/gcn3/SConsopts b/src/arch/amdgpu/gcn3/SConsopts
index 92bde97..3312e98 100644
--- a/src/arch/amdgpu/gcn3/SConsopts
+++ b/src/arch/amdgpu/gcn3/SConsopts
@@ -33,4 +33,4 @@
Import('*')
-all_gpu_isa_list.append('gcn3')
+main.Append(ALL_GPU_ISAS=['gcn3'])
diff --git a/src/arch/amdgpu/vega/SConsopts b/src/arch/amdgpu/vega/SConsopts
index 0e44e37..b2b6695 100644
--- a/src/arch/amdgpu/vega/SConsopts
+++ b/src/arch/amdgpu/vega/SConsopts
@@ -33,4 +33,4 @@
Import('*')
-all_gpu_isa_list.append('vega')
+main.Append(ALL_GPU_ISAS=['vega'])
diff --git a/src/arch/arm/SConsopts b/src/arch/arm/SConsopts
index 020e499..c284f2c 100644
--- a/src/arch/arm/SConsopts
+++ b/src/arch/arm/SConsopts
@@ -28,4 +28,4 @@
Import('*')
-all_isa_list.append('arm')
+main.Append(ALL_ISAS=['arm'])
diff --git a/src/arch/mips/SConsopts b/src/arch/mips/SConsopts
index ee4d236..58240c1 100644
--- a/src/arch/mips/SConsopts
+++ b/src/arch/mips/SConsopts
@@ -28,4 +28,4 @@
Import('*')
-all_isa_list.append('mips')
+main.Append(ALL_ISAS=['mips'])
diff --git a/src/arch/null/SConsopts b/src/arch/null/SConsopts
index a799754..6355ce3 100644
--- a/src/arch/null/SConsopts
+++ b/src/arch/null/SConsopts
@@ -37,4 +37,4 @@
Import('*')
-all_isa_list.append('null')
+main.Append(ALL_ISAS=['null'])
diff --git a/src/arch/power/SConsopts b/src/arch/power/SConsopts
index 851f2ba..cb136fe 100644
--- a/src/arch/power/SConsopts
+++ b/src/arch/power/SConsopts
@@ -28,4 +28,4 @@
Import('*')
-all_isa_list.append('power')
+main.Append(ALL_ISAS=['power'])
diff --git a/src/arch/riscv/SConsopts b/src/arch/riscv/SConsopts
index f5a8de5..76713ee 100644
--- a/src/arch/riscv/SConsopts
+++ b/src/arch/riscv/SConsopts
@@ -28,4 +28,4 @@
Import('*')
-all_isa_list.append('riscv')
+main.Append(ALL_ISAS=['riscv'])
diff --git a/src/arch/sparc/SConsopts b/src/arch/sparc/SConsopts
index 41aa275..48fb4a6 100644
--- a/src/arch/sparc/SConsopts
+++ b/src/arch/sparc/SConsopts
@@ -28,4 +28,4 @@
Import('*')
-all_isa_list.append('sparc')
+main.Append(ALL_ISAS=['sparc'])
diff --git a/src/arch/x86/SConsopts b/src/arch/x86/SConsopts
index 006d009..93dff8c 100644
--- a/src/arch/x86/SConsopts
+++ b/src/arch/x86/SConsopts
@@ -28,4 +28,4 @@
Import('*')
-all_isa_list.append('x86')
+main.Append(ALL_ISAS=['x86'])
diff --git a/src/cpu/SConsopts b/src/cpu/SConsopts
index af35a20..c39d1eb 100644
--- a/src/cpu/SConsopts
+++ b/src/cpu/SConsopts
@@ -25,12 +25,7 @@
Import('*')
-def CpuModel(name):
- main.Append(ALL_CPU_MODELS=[name])
-
-Export('CpuModel')
-
def add_cpu_models_var():
sticky_vars.Add(ListVariable('CPU_MODELS', 'CPU models', [],
- set(main.get('ALL_CPU_MODELS', []))))
+ sorted(set(main.Split('${ALL_CPU_MODELS}')))))
AfterSConsopts(add_cpu_models_var)
diff --git a/src/cpu/checker/SConsopts b/src/cpu/checker/SConsopts
index f949d2a..5a7a873 100644
--- a/src/cpu/checker/SConsopts
+++ b/src/cpu/checker/SConsopts
@@ -28,4 +28,4 @@
Import('*')
-CpuModel('CheckerCPU')
+main.Append(ALL_CPU_MODELS=['CheckerCPU'])
diff --git a/src/cpu/minor/SConsopts b/src/cpu/minor/SConsopts
index 9169ee9..16ff599 100644
--- a/src/cpu/minor/SConsopts
+++ b/src/cpu/minor/SConsopts
@@ -37,4 +37,4 @@
Import('*')
-CpuModel('MinorCPU')
+main.Append(ALL_CPU_MODELS=['MinorCPU'])
diff --git a/src/cpu/o3/SConsopts b/src/cpu/o3/SConsopts
index 0c0c56c..3479484 100644
--- a/src/cpu/o3/SConsopts
+++ b/src/cpu/o3/SConsopts
@@ -28,4 +28,4 @@
Import('*')
-CpuModel('O3CPU')
+main.Append(ALL_CPU_MODELS=['O3CPU'])
diff --git a/src/cpu/simple/SConsopts b/src/cpu/simple/SConsopts
index 5ebdf30..f12fee2 100644
--- a/src/cpu/simple/SConsopts
+++ b/src/cpu/simple/SConsopts
@@ -28,5 +28,4 @@
Import('*')
-CpuModel('AtomicSimpleCPU')
-CpuModel('TimingSimpleCPU')
+main.Append(ALL_CPU_MODELS=['AtomicSimpleCPU', 'TimingSimpleCPU'])
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4135709f5bceee959b5178a4700656aa782b1d6b
Gerrit-Change-Number: 48965
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-CC: Hoa Nguyen <[email protected]>
Gerrit-MessageType: merged
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