[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Adopt the default implementations of TC *Reg funcs.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49112 )

Change subject: fastmodel: Adopt the default implementations of TC *Reg  
funcs.
......................................................................

fastmodel: Adopt the default implementations of TC *Reg funcs.

The ThreadContext methods for the fast model are not on the critical
path and so aren't performance sensitive, and this will avoid having to
reorganize the readIntReg, etc, functions to use the new scheme. That
can be done down the line.

Change-Id: Icb9196815ce5a07edae333f19d2ea120015aaf1a
---
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
2 files changed, 112 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc
index 11e4f17..d66d3bb 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -619,6 +619,106 @@
 }

 RegVal
+ThreadContext::getReg(const RegId &reg) const
+{
+    return getRegFlat(flattenRegId(reg));
+}
+
+void
+ThreadContext::setReg(const RegId &reg, RegVal val)
+{
+    setRegFlat(flattenRegId(reg), val);
+}
+
+void
+ThreadContext::getReg(const RegId &reg, void *val) const
+{
+    getRegFlat(flattenRegId(reg), val);
+}
+
+void
+ThreadContext::setReg(const RegId &reg, const void *val)
+{
+    setRegFlat(flattenRegId(reg), val);
+}
+
+RegVal
+ThreadContext::getRegFlat(const RegId &reg) const
+{
+    RegVal val;
+    getRegFlat(reg, &val);
+    return val;
+}
+
+void
+ThreadContext::setRegFlat(const RegId &reg, RegVal val)
+{
+    setRegFlat(reg, &val);
+}
+
+void
+ThreadContext::getRegFlat(const RegId &reg, void *val) const
+{
+    const RegIndex idx = reg.index();
+    const RegClassType type = reg.classValue();
+    switch (type) {
+      case IntRegClass:
+        *(RegVal *)val = readIntRegFlat(idx);
+        break;
+      case FloatRegClass:
+        *(RegVal *)val = readFloatRegFlat(idx);
+        break;
+      case VecRegClass:
+        *(ArmISA::VecRegContainer *)val = readVecRegFlat(idx);
+        break;
+      case VecPredRegClass:
+        *(ArmISA::VecPredRegContainer *)val = readVecPredRegFlat(idx);
+        break;
+      case CCRegClass:
+        *(RegVal *)val = readCCRegFlat(idx);
+        break;
+      case MiscRegClass:
+        panic("MiscRegs should not be read with getReg.");
+      case VecElemClass:
+        *(ArmISA::VecElem *)val = readVecElemFlat(idx, reg.elemIndex());
+        break;
+      default:
+        panic("Unrecognized register class type %d.", type);
+    }
+}
+
+void
+ThreadContext::setRegFlat(const RegId &reg, const void *val)
+{
+    const RegIndex idx = reg.index();
+    const RegClassType type = reg.classValue();
+    switch (type) {
+      case IntRegClass:
+        setIntRegFlat(idx, *(RegVal *)val);
+        break;
+      case FloatRegClass:
+        setFloatRegFlat(idx, *(RegVal *)val);
+        break;
+      case VecRegClass:
+        setVecRegFlat(idx, *(ArmISA::VecRegContainer *)val);
+        break;
+      case VecPredRegClass:
+        setVecPredRegFlat(idx, *(ArmISA::VecPredRegContainer *)val);
+        break;
+      case CCRegClass:
+        setCCRegFlat(idx, *(RegVal *)val);
+        break;
+      case MiscRegClass:
+        panic("MiscRegs should not be read with getReg.");
+      case VecElemClass:
+        setVecElemFlat(idx, reg.elemIndex(), *(ArmISA::VecElem *)val);
+        break;
+      default:
+        panic("Unrecognized register class type %d.", type);
+    }
+}
+
+RegVal
 ThreadContext::readIntReg(RegIndex reg_idx) const
 {
     ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh  
b/src/arch/arm/fastmodel/iris/thread_context.hh
index 49f2cae..b8e60a7 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -277,6 +277,12 @@
     //
     // New accessors for new decoder.
     //
+    RegVal getReg(const RegId &reg) const override;
+    void getReg(const RegId &reg, void *val) const override;
+
+    void setReg(const RegId &reg, RegVal val) override;
+    void setReg(const RegId &reg, const void *val) override;
+
     RegVal readIntReg(RegIndex reg_idx) const override;

     RegVal
@@ -399,6 +405,12 @@
      * serialization code to access all registers.
      */

+    RegVal getRegFlat(const RegId &reg) const override;
+    void getRegFlat(const RegId &reg, void *val) const override;
+
+    void setRegFlat(const RegId &reg, RegVal val) override;
+    void setRegFlat(const RegId &reg, const void *val) override;
+
     RegVal readIntRegFlat(RegIndex idx) const override;
     void setIntRegFlat(RegIndex idx, uint64_t val) override;


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icb9196815ce5a07edae333f19d2ea120015aaf1a
Gerrit-Change-Number: 49112
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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