Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49128 )
Change subject: cpu: Simplify or eliminate set${type}Result methods for o3
and checker.
......................................................................
cpu: Simplify or eliminate set${type}Result methods for o3 and checker.
These methods are all identical now. The O3 versions can all be
consolidated into a single method. For the checker CPU, they can
actually be eliminated entirely, and the result queue's "emplace()"
method can be used to add items using less text than just calling the
original helper method.
Change-Id: Ifaeb3beeea257c8bbf951ee1dd8d2d5fd8bb3964
---
M src/cpu/checker/cpu.hh
M src/cpu/o3/dyn_inst.hh
2 files changed, 14 insertions(+), 56 deletions(-)
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 66e48af..62ac9a5 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -250,34 +250,13 @@
return thread->readCCReg(reg.index());
}
- template<typename T>
- void
- setScalarResult(T&& t)
- {
- result.push(InstResult(std::forward<T>(t)));
- }
-
- template<typename T>
- void
- setVecResult(T&& t)
- {
- result.push(InstResult(std::forward<T>(t)));
- }
-
- template<typename T>
- void
- setVecPredResult(T&& t)
- {
- result.push(InstResult(std::forward<T>(t)));
- }
-
void
setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(IntRegClass));
thread->setIntReg(reg.index(), val);
- setScalarResult(val);
+ result.emplace(val);
}
void
@@ -286,7 +265,7 @@
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(FloatRegClass));
thread->setFloatReg(reg.index(), val);
- setScalarResult(val);
+ result.emplace(val);
}
void
@@ -295,7 +274,7 @@
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(CCRegClass));
thread->setCCReg(reg.index(), val);
- setScalarResult((uint64_t)val);
+ result.emplace(val);
}
void
@@ -305,7 +284,7 @@
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(VecRegClass));
thread->setVecReg(reg, val);
- setVecResult(val);
+ result.emplace(val);
}
void
@@ -314,7 +293,7 @@
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(VecElemClass));
thread->setVecElem(reg, val);
- setScalarResult(val);
+ result.emplace(val);
}
void setVecPredRegOperand(const StaticInst *si, int idx,
@@ -323,7 +302,7 @@
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(VecPredRegClass));
thread->setVecPredReg(reg, val);
- setVecPredResult(val);
+ result.emplace(val);
}
bool readPredicate() const override { return thread->readPredicate(); }
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 24c34b0..f26ea22 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -771,33 +771,12 @@
/** Pushes a result onto the instResult queue. */
/** @{ */
- /** Scalar result. */
template<typename T>
void
- setScalarResult(T &&t)
+ setResult(T &&t)
{
if (instFlags[RecordResult]) {
- instResult.push(InstResult(std::forward<T>(t)));
- }
- }
-
- /** Full vector result. */
- template<typename T>
- void
- setVecResult(T &&t)
- {
- if (instFlags[RecordResult]) {
- instResult.push(InstResult(std::forward<T>(t)));
- }
- }
-
- /** Predicate result. */
- template<typename T>
- void
- setVecPredResult(T &&t)
- {
- if (instFlags[RecordResult]) {
- instResult.push(InstResult(std::forward<T>(t)));
+ instResult.emplace(std::forward<T>(t));
}
}
/** @} */
@@ -1273,14 +1252,14 @@
setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
this->cpu->setIntReg(this->regs.renamedDestIdx(idx), val);
- setScalarResult(val);
+ setResult(val);
}
void
setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
override
{
this->cpu->setFloatReg(this->regs.renamedDestIdx(idx), val);
- setScalarResult(val);
+ setResult(val);
}
void
@@ -1288,7 +1267,7 @@
const TheISA::VecRegContainer& val) override
{
this->cpu->setVecReg(this->regs.renamedDestIdx(idx), val);
- setVecResult(val);
+ setResult(val);
}
void
@@ -1296,7 +1275,7 @@
{
int reg_idx = idx;
this->cpu->setVecElem(this->regs.renamedDestIdx(reg_idx), val);
- setScalarResult(val);
+ setResult(val);
}
void
@@ -1304,14 +1283,14 @@
const TheISA::VecPredRegContainer& val) override
{
this->cpu->setVecPredReg(this->regs.renamedDestIdx(idx), val);
- setVecPredResult(val);
+ setResult(val);
}
void
setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
this->cpu->setCCReg(this->regs.renamedDestIdx(idx), val);
- setScalarResult(val);
+ setResult(val);
}
};
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49128
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifaeb3beeea257c8bbf951ee1dd8d2d5fd8bb3964
Gerrit-Change-Number: 49128
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
