Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49125 )
Change subject: cpu: Stop treating VecElem as its own case in InstResult.
......................................................................
cpu: Stop treating VecElem as its own case in InstResult.
Since this is now a RegVal, we can treat it as a Scalar result.
Change-Id: I0afd7815c1ebf20b50ce27a00b27bb408d2a32ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49125
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/cpu/checker/cpu.hh
M src/cpu/checker/cpu_impl.hh
M src/cpu/inst_res.hh
M src/cpu/o3/dyn_inst.hh
4 files changed, 6 insertions(+), 41 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index ef61d80..4ed21f5 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -262,14 +262,6 @@
template<typename T>
void
- setVecElemResult(T&& t)
- {
- result.push(InstResult(std::forward<T>(t),
- InstResult::ResultType::VecElem));
- }
-
- template<typename T>
- void
setVecPredResult(T&& t)
{
result.push(InstResult(std::forward<T>(t),
@@ -319,7 +311,7 @@
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(VecElemClass));
thread->setVecElem(reg, val);
- setVecElemResult(val);
+ setScalarResult(val);
}
void
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index b7cb6b3..26c22a5 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -603,9 +603,8 @@
thread->setVecReg(idx, mismatch_val.asVector());
break;
case VecElemClass:
- panic_if(!mismatch_val.isVecElem(),
- "Unexpected type of result");
- thread->setVecElem(idx, mismatch_val.asVectorElem());
+ panic_if(!mismatch_val.isScalar(), "Unexpected type of
result");
+ thread->setVecElem(idx, mismatch_val.asInteger());
break;
case CCRegClass:
panic_if(!mismatch_val.isScalar(), "Unexpected type of
result");
@@ -638,8 +637,8 @@
thread->setVecReg(idx, res.asVector());
break;
case VecElemClass:
- panic_if(!res.isVecElem(), "Unexpected type of result");
- thread->setVecElem(idx, res.asVectorElem());
+ panic_if(!res.isScalar(), "Unexpected type of result");
+ thread->setVecElem(idx, res.asInteger());
break;
case CCRegClass:
panic_if(!res.isScalar(), "Unexpected type of result");
diff --git a/src/cpu/inst_res.hh b/src/cpu/inst_res.hh
index da11072..5bef0da 100644
--- a/src/cpu/inst_res.hh
+++ b/src/cpu/inst_res.hh
@@ -54,7 +54,6 @@
RegVal integer;
double dbl;
TheISA::VecRegContainer vector;
- RegVal vecElem;
TheISA::VecPredRegContainer pred;
MultiResult() {}
};
@@ -62,7 +61,6 @@
enum class ResultType
{
Scalar,
- VecElem,
VecReg,
VecPredReg,
NumResultTypes,
@@ -115,9 +113,6 @@
case ResultType::Scalar:
result.integer = that.result.integer;
break;
- case ResultType::VecElem:
- result.vecElem = that.result.vecElem;
- break;
case ResultType::VecReg:
result.vector = that.result.vector;
break;
@@ -144,8 +139,6 @@
switch (type) {
case ResultType::Scalar:
return result.integer == that.result.integer;
- case ResultType::VecElem:
- return result.vecElem == that.result.vecElem;
case ResultType::VecReg:
return result.vector == that.result.vector;
case ResultType::VecPredReg:
@@ -169,8 +162,6 @@
bool isScalar() const { return type == ResultType::Scalar; }
/** Is this a vector result?. */
bool isVector() const { return type == ResultType::VecReg; }
- /** Is this a vector element result?. */
- bool isVecElem() const { return type == ResultType::VecElem; }
/** Is this a predicate result?. */
bool isPred() const { return type == ResultType::VecPredReg; }
/** Is this a valid result?. */
@@ -201,12 +192,6 @@
panic_if(!isVector(), "Converting scalar (or invalid) to
vector!!");
return result.vector;
}
- const RegVal&
- asVectorElem() const
- {
- panic_if(!isVecElem(), "Converting scalar (or invalid) to
vector!!");
- return result.vecElem;
- }
const TheISA::VecPredRegContainer&
asPred() const
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 7c5cee0..a23be38 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -793,17 +793,6 @@
}
}
- /** Vector element result. */
- template<typename T>
- void
- setVecElemResult(T &&t)
- {
- if (instFlags[RecordResult]) {
- instResult.push(InstResult(std::forward<T>(t),
- InstResult::ResultType::VecElem));
- }
- }
-
/** Predicate result. */
template<typename T>
void
@@ -1310,7 +1299,7 @@
{
int reg_idx = idx;
this->cpu->setVecElem(this->regs.renamedDestIdx(reg_idx), val);
- setVecElemResult(val);
+ setScalarResult(val);
}
void
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0afd7815c1ebf20b50ce27a00b27bb408d2a32ab
Gerrit-Change-Number: 49125
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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