Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49124 )
Change subject: cpu: Use RegVal for VecElems instead of TheISA::VecElem.
......................................................................
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
If VecElem is a basic type, which is a reasonable assumption, it can be
contained in a RegVal. We still need to use the TheISA::VecElem type to
extract it from an actual vector, but then it can be passed around as a
RegVal.
Change-Id: I4dc470e7cc369499ce3686dd291eb3d93ca0819a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49124
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/fastmodel/iris/thread_context.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/inst_res.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.cc
M src/cpu/o3/thread_context.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
15 files changed, 48 insertions(+), 54 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh
b/src/arch/arm/fastmodel/iris/thread_context.hh
index 49f2cae..8be9281 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -292,7 +292,7 @@
panic("%s not implemented.", __FUNCTION__);
}
- const ArmISA::VecElem &
+ RegVal
readVecElem(const RegId ®) const override
{
panic("%s not implemented.", __FUNCTION__);
@@ -327,7 +327,7 @@
}
void
- setVecElem(const RegId& reg, const ArmISA::VecElem& val) override
+ setVecElem(const RegId& reg, RegVal val) override
{
panic("%s not implemented.", __FUNCTION__);
}
@@ -425,14 +425,13 @@
panic("%s not implemented.", __FUNCTION__);
}
- const ArmISA::VecElem&
+ RegVal
readVecElemFlat(RegIndex idx, const ElemIndex& elemIdx) const override
{
panic("%s not implemented.", __FUNCTION__);
}
void
- setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx,
- const ArmISA::VecElem &val) override
+ setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx, RegVal val)
override
{
panic("%s not implemented.", __FUNCTION__);
}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index f902df4..ef61d80 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -213,7 +213,7 @@
return thread->getWritableVecReg(reg);
}
- TheISA::VecElem
+ RegVal
readVecElemOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -314,8 +314,7 @@
}
void
- setVecElemOperand(const StaticInst *si, int idx,
- const TheISA::VecElem val) override
+ setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(VecElemClass));
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index 872c670..8618712 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -253,7 +253,7 @@
return actualTC->getWritableVecReg(reg);
}
- const TheISA::VecElem &
+ RegVal
readVecElem(const RegId& reg) const override
{
return actualTC->readVecElem(reg);
@@ -299,7 +299,7 @@
}
void
- setVecElem(const RegId& reg, const TheISA::VecElem& val) override
+ setVecElem(const RegId& reg, RegVal val) override
{
actualTC->setVecElem(reg, val);
checkerTC->setVecElem(reg, val);
@@ -449,7 +449,7 @@
actualTC->setVecRegFlat(idx, val);
}
- const TheISA::VecElem &
+ RegVal
readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
{
return actualTC->readVecElemFlat(idx, elem_idx);
@@ -457,7 +457,7 @@
void
setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
- const TheISA::VecElem& val) override
+ RegVal val) override
{
actualTC->setVecElemFlat(idx, elem_idx, val);
}
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 66b43b1..8550815 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -123,12 +123,11 @@
/** Vector Elem Interfaces. */
/** @{ */
/** Reads an element of a vector register. */
- virtual TheISA::VecElem readVecElemOperand(
- const StaticInst *si, int idx) const = 0;
+ virtual RegVal readVecElemOperand(const StaticInst *si, int idx) const
= 0;
/** Sets a vector register to a value. */
virtual void setVecElemOperand(
- const StaticInst *si, int idx, const TheISA::VecElem val) = 0;
+ const StaticInst *si, int idx, RegVal val) = 0;
/** @} */
/** Predicate registers interface. */
diff --git a/src/cpu/inst_res.hh b/src/cpu/inst_res.hh
index e1151eb..da11072 100644
--- a/src/cpu/inst_res.hh
+++ b/src/cpu/inst_res.hh
@@ -41,6 +41,7 @@
#include <type_traits>
#include "arch/generic/vec_reg.hh"
+#include "base/types.hh"
namespace gem5
{
@@ -50,10 +51,10 @@
public:
union MultiResult
{
- uint64_t integer;
+ RegVal integer;
double dbl;
TheISA::VecRegContainer vector;
- TheISA::VecElem vecElem;
+ RegVal vecElem;
TheISA::VecPredRegContainer pred;
MultiResult() {}
};
@@ -200,7 +201,7 @@
panic_if(!isVector(), "Converting scalar (or invalid) to
vector!!");
return result.vector;
}
- const TheISA::VecElem&
+ const RegVal&
asVectorElem() const
{
panic_if(!isVecElem(), "Converting scalar (or invalid) to
vector!!");
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index d68c359..6d94e47 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -176,7 +176,7 @@
return thread.getWritableVecReg(reg);
}
- TheISA::VecElem
+ RegVal
readVecElemOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -235,8 +235,7 @@
}
void
- setVecElemOperand(const StaticInst *si, int idx,
- const TheISA::VecElem val) override
+ setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(VecElemClass));
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 1743857..8f0c531 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1170,7 +1170,7 @@
return regFile.getWritableVecReg(phys_reg);
}
-const TheISA::VecElem&
+RegVal
CPU::readVecElem(PhysRegIdPtr phys_reg) const
{
cpuStats.vecRegfileReads++;
@@ -1220,7 +1220,7 @@
}
void
-CPU::setVecElem(PhysRegIdPtr phys_reg, const TheISA::VecElem& val)
+CPU::setVecElem(PhysRegIdPtr phys_reg, RegVal val)
{
cpuStats.vecRegfileWrites++;
regFile.setVecElem(phys_reg, val);
@@ -1277,7 +1277,7 @@
return getWritableVecReg(phys_reg);
}
-const TheISA::VecElem&
+RegVal
CPU::readArchVecElem(
const RegIndex& reg_idx, const ElemIndex& ldx, ThreadID tid) const
{
@@ -1343,7 +1343,7 @@
void
CPU::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
- const TheISA::VecElem& val, ThreadID tid)
+ RegVal val, ThreadID tid)
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecElemClass, reg_idx, ldx));
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 412bb18..6a02cb8 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -346,7 +346,7 @@
vecMode = vec_mode;
}
- const TheISA::VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
+ RegVal readVecElem(PhysRegIdPtr reg_idx) const;
const TheISA::VecPredRegContainer&
readVecPredReg(PhysRegIdPtr reg_idx) const;
@@ -361,7 +361,7 @@
void setVecReg(PhysRegIdPtr reg_idx, const TheISA::VecRegContainer&
val);
- void setVecElem(PhysRegIdPtr reg_idx, const TheISA::VecElem& val);
+ void setVecElem(PhysRegIdPtr reg_idx, RegVal val);
void setVecPredReg(PhysRegIdPtr reg_idx,
const TheISA::VecPredRegContainer& val);
@@ -377,7 +377,7 @@
/** Read architectural vector register for modification. */
TheISA::VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID
tid);
- const TheISA::VecElem& readArchVecElem(const RegIndex& reg_idx,
+ RegVal readArchVecElem(const RegIndex& reg_idx,
const ElemIndex& ldx, ThreadID tid) const;
const TheISA::VecPredRegContainer& readArchVecPredReg(
@@ -404,7 +404,7 @@
ThreadID tid);
void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
- const TheISA::VecElem& val, ThreadID tid);
+ RegVal val, ThreadID tid);
void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 79263dc..7c5cee0 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -1255,7 +1255,7 @@
return
this->cpu->getWritableVecReg(this->regs.renamedDestIdx(idx));
}
- TheISA::VecElem
+ RegVal
readVecElemOperand(const StaticInst *si, int idx) const override
{
return this->cpu->readVecElem(this->regs.renamedSrcIdx(idx));
@@ -1306,8 +1306,7 @@
}
void
- setVecElemOperand(const StaticInst *si, int idx,
- const TheISA::VecElem val) override
+ setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
{
int reg_idx = idx;
this->cpu->setVecElem(this->regs.renamedDestIdx(reg_idx), val);
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 8101d53..a141d49 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -226,12 +226,12 @@
}
/** Reads a vector element. */
- const TheISA::VecElem &
+ RegVal
readVecElem(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->is(VecElemClass));
auto ret = vectorRegFile[phys_reg->index()].as<TheISA::VecElem>();
- const TheISA::VecElem& val = ret[phys_reg->elemIndex()];
+ RegVal val = ret[phys_reg->elemIndex()];
DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
" has data %#x\n", phys_reg->elemIndex(),
int(phys_reg->index()), val);
@@ -311,7 +311,7 @@
/** Sets a vector register to the given value. */
void
- setVecElem(PhysRegIdPtr phys_reg, const TheISA::VecElem val)
+ setVecElem(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->is(VecElemClass));
diff --git a/src/cpu/o3/thread_context.cc b/src/cpu/o3/thread_context.cc
index 0fbdf67..0bf4324 100644
--- a/src/cpu/o3/thread_context.cc
+++ b/src/cpu/o3/thread_context.cc
@@ -176,7 +176,7 @@
return cpu->getWritableArchVecReg(reg_id, thread->threadId());
}
-const TheISA::VecElem&
+RegVal
ThreadContext::readVecElemFlat(RegIndex idx, const ElemIndex& elemIndex)
const
{
return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
@@ -227,7 +227,7 @@
void
ThreadContext::setVecElemFlat(RegIndex idx,
- const ElemIndex& elemIndex, const TheISA::VecElem& val)
+ const ElemIndex& elemIndex, RegVal val)
{
cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
conditionalSquash();
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 759785b..d61c07f 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -212,7 +212,7 @@
return getWritableVecRegFlat(flattenRegId(id).index());
}
- const TheISA::VecElem &
+ RegVal
readVecElem(const RegId& reg) const override
{
return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
@@ -258,7 +258,7 @@
}
void
- setVecElem(const RegId& reg, const TheISA::VecElem& val) override
+ setVecElem(const RegId& reg, RegVal val) override
{
setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
}
@@ -372,10 +372,10 @@
void setVecRegFlat(RegIndex idx,
const TheISA::VecRegContainer& val) override;
- const TheISA::VecElem &readVecElemFlat(RegIndex idx,
+ RegVal readVecElemFlat(RegIndex idx,
const ElemIndex& elemIndex) const override;
void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
- const TheISA::VecElem& val) override;
+ RegVal val) override;
const TheISA::VecPredRegContainer&
readVecPredRegFlat(RegIndex idx) const override;
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 7614491..53b5735 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -362,7 +362,7 @@
}
/** Reads an element of a vector register. */
- TheISA::VecElem
+ RegVal
readVecElemOperand(const StaticInst *si, int idx) const override
{
execContextStats.numVecRegReads++;
@@ -373,8 +373,7 @@
/** Sets an element of a vector register to a value. */
void
- setVecElemOperand(const StaticInst *si, int idx,
- const TheISA::VecElem val) override
+ setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
{
execContextStats.numVecRegWrites++;
const RegId& reg = si->destRegIdx(idx);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 37f666c..feec42f 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -306,13 +306,12 @@
return regVal;
}
- const TheISA::VecElem &
+ RegVal
readVecElem(const RegId ®) const override
{
int flatIndex = isa->flattenVecElemIndex(reg.index());
assert(flatIndex < vecRegs.size());
- const TheISA::VecElem& regVal =
- readVecElemFlat(flatIndex, reg.elemIndex());
+ RegVal regVal = readVecElemFlat(flatIndex, reg.elemIndex());
DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
" %#x.\n", reg.elemIndex(), reg.index(), flatIndex,
regVal);
return regVal;
@@ -389,7 +388,7 @@
}
void
- setVecElem(const RegId ®, const TheISA::VecElem &val) override
+ setVecElem(const RegId ®, RegVal val) override
{
int flatIndex = isa->flattenVecElemIndex(reg.index());
assert(flatIndex < vecRegs.size());
@@ -520,7 +519,7 @@
vecRegs[reg] = val;
}
- const TheISA::VecElem &
+ RegVal
readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const
override
{
return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
@@ -528,7 +527,7 @@
void
setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
- const TheISA::VecElem &val) override
+ RegVal val) override
{
vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
}
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index bbe084a..3ae8a7f 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -200,7 +200,7 @@
readVecReg(const RegId& reg) const = 0;
virtual TheISA::VecRegContainer& getWritableVecReg(const RegId& reg) =
0;
- virtual const TheISA::VecElem& readVecElem(const RegId& reg) const = 0;
+ virtual RegVal readVecElem(const RegId& reg) const = 0;
virtual const TheISA::VecPredRegContainer& readVecPredReg(
const RegId& reg) const = 0;
@@ -216,7 +216,7 @@
virtual void setVecReg(const RegId& reg,
const TheISA::VecRegContainer& val) = 0;
- virtual void setVecElem(const RegId& reg, const TheISA::VecElem& val)
= 0;
+ virtual void setVecElem(const RegId& reg, RegVal val) = 0;
virtual void setVecPredReg(const RegId& reg,
const TheISA::VecPredRegContainer& val) = 0;
@@ -291,10 +291,10 @@
virtual void setVecRegFlat(RegIndex idx,
const TheISA::VecRegContainer& val) = 0;
- virtual const TheISA::VecElem& readVecElemFlat(RegIndex idx,
+ virtual RegVal readVecElemFlat(RegIndex idx,
const ElemIndex& elem_idx) const = 0;
virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
- const TheISA::VecElem& val) = 0;
+ RegVal val) = 0;
virtual const TheISA::VecPredRegContainer &
readVecPredRegFlat(RegIndex idx) const = 0;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49124
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4dc470e7cc369499ce3686dd291eb3d93ca0819a
Gerrit-Change-Number: 49124
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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