Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49345 )
Change subject: configs: Move some runtime checks in components
......................................................................
configs: Move some runtime checks in components
The runtime coherence check should check the cache heirarchy, not the
global protocol so it can differentiate between Ruby and classic.
This patch also removes some unnecessary includes and fails earlier in
MESI_Two_Level if that protocol isn't built.
Change-Id: I31c1fbd1d9597163b9138e80619d05c132a91545
Signed-off-by: Jason Lowe-Power <[email protected]>
---
M components_library/boards/abstract_board.py
M components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
M components_library/processors/simple_processor.py
3 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/components_library/boards/abstract_board.py
b/components_library/boards/abstract_board.py
index 653c589..4bece04 100644
--- a/components_library/boards/abstract_board.py
+++ b/components_library/boards/abstract_board.py
@@ -29,9 +29,6 @@
from m5.objects import System, Port, IOXBar, ClockDomain
-from ..isas import ISA
-from ..coherence_protocol import CoherenceProtocol
-
from typing import List
diff --git
a/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
b/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
index cc643e5..0650613 100644
---
a/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++
b/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
@@ -67,6 +67,16 @@
l2_assoc: str,
num_l2_banks: int,
):
+
+ if (
+ get_runtime_coherence_protocol()
+ != CoherenceProtocol.MESI_TWO_LEVEL
+ ):
+ raise EnvironmentError(
+ "The MESITwoLevelCacheHierarchy must be used with with
the "
+ "MESI_Two_Level coherence protocol."
+ )
+
AbstractRubyCacheHierarchy.__init__(self=self)
AbstractTwoLevelCacheHierarchy.__init__(
self,
@@ -81,15 +91,6 @@
self._num_l2_banks = num_l2_banks
def incorporate_cache(self, board: AbstractBoard) -> None:
- if (
- get_runtime_coherence_protocol()
- != CoherenceProtocol.MESI_TWO_LEVEL
- ):
- raise EnvironmentError(
- "The MESITwoLevelCacheHierarchy must be used with with
the "
- "MESI_Two_Level coherence protocol."
- )
-
cache_line_size = board.get_cache_line_size()
self.ruby_system = RubySystem()
diff --git a/components_library/processors/simple_processor.py
b/components_library/processors/simple_processor.py
index 4b45171..e449173 100644
--- a/components_library/processors/simple_processor.py
+++ b/components_library/processors/simple_processor.py
@@ -34,8 +34,6 @@
from .abstract_processor import AbstractProcessor
from .cpu_types import CPUTypes
from ..boards.abstract_board import AbstractBoard
-from ..coherence_protocol import is_ruby
-from ..runtime import get_runtime_coherence_protocol
from typing import List
@@ -79,7 +77,7 @@
elif self._cpu_type == CPUTypes.KVM:
board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
elif self._cpu_type == CPUTypes.ATOMIC:
- if is_ruby(get_runtime_coherence_protocol()):
+ if board.get_cache_hierarchy().is_ruby():
warn(
"Using an atomic core with Ruby will result in "
"'atomic_noncaching' memory mode. This will skip
caching "
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I31c1fbd1d9597163b9138e80619d05c132a91545
Gerrit-Change-Number: 49345
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: newchange
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