[gem5-dev] Change in gem5/gem5[develop]: configs: Update how private L1/L2 cache handles MMU

[Jason Lowe-Power (Gerrit) via gem5-dev]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49364 )

Change subject: configs: Update how private L1/L2 cache handles MMU
......................................................................

configs: Update how private L1/L2 cache handles MMU

This change makes an MMU cache per TLB port as is required by x86 and
RISC-V.

Change-Id: I79cf82ab18d31b81d3ec7060501f2642f21b630b
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M components_library/cachehierarchies/classic/caches/mmu_cache.py
M  
components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
2 files changed, 19 insertions(+), 4 deletions(-)



diff --git  
a/components_library/cachehierarchies/classic/caches/mmu_cache.py  
b/components_library/cachehierarchies/classic/caches/mmu_cache.py
index 23707e0..8c72674 100644
--- a/components_library/cachehierarchies/classic/caches/mmu_cache.py
+++ b/components_library/cachehierarchies/classic/caches/mmu_cache.py
@@ -46,7 +46,6 @@
         mshrs: Optional[int] = 20,
         tgts_per_mshr: Optional[int] = 12,
         writeback_clean: Optional[bool] = True,
-        prefetcher: BasePrefetcher = StridePrefetcher(),
     ):
         super(MMUCache, self).__init__()
         self.size = size
@@ -57,4 +56,3 @@
         self.mshrs = mshrs
         self.tgts_per_mshr = tgts_per_mshr
         self.writeback_clean = writeback_clean
-        self.prefetcher = prefetcher
diff --git  
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py  
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
index a2a10fc..6d9c603 100644
---  
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
+++  
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
@@ -30,11 +30,12 @@
 from .caches.l1dcache import L1DCache
 from .caches.l1icache import L1ICache
 from .caches.l2cache import L2Cache
+from .caches.mmu_cache import MMUCache
 from ...boards.abstract_board import AbstractBoard
 from ...isas import ISA
 from ...runtime import get_runtime_isa

-from m5.objects import L2XBar, BaseXBar, SystemXBar, BadAddr, Port
+from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port

 from ...utils.override import *

@@ -136,6 +137,19 @@
             L2Cache(size=self._l2_size)
             for i in range(board.get_processor().get_num_cores())
         ]
+        # ITLB Page walk caches
+        self.iptw_caches = [
+            MMUCache(size='8KiB')
+            for _ in range(board.get_processor().get_num_cores())
+        ]
+        # DTLB Page walk caches
+        self.dptw_caches = [
+            MMUCache(size='8KiB')
+            for _ in range(board.get_processor().get_num_cores())
+        ]
+
+        if board.has_coherent_io():
+            self._setup_io_cache(board)

         for i, cpu in enumerate(board.get_processor().get_cores()):

@@ -144,13 +158,15 @@

             self.l1icaches[i].mem_side = self.l2buses[i].cpu_side_ports
             self.l1dcaches[i].mem_side = self.l2buses[i].cpu_side_ports
+            self.iptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports
+            self.dptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports

             self.l2buses[i].mem_side_ports = self.l2caches[i].cpu_side

             self.membus.cpu_side_ports = self.l2caches[i].mem_side

             cpu.connect_walker_ports(
-                self.membus.cpu_side_ports, self.membus.cpu_side_ports
+                self.iptw_caches[i].cpu_side, self.dptw_caches[i].cpu_side
             )

             if get_runtime_isa() == ISA.X86:
@@ -159,6 +175,7 @@
                 cpu.connect_interrupt(int_req_port, int_resp_port)
             else:
                 cpu.connect_interrupt()
+
     def _setup_io_cache(self, board: AbstractBoard) -> None:
         """Create a cache for coherent I/O connections"""
         self.iocache = Cache(

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I79cf82ab18d31b81d3ec7060501f2642f21b630b
Gerrit-Change-Number: 49364
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <power...@gmail.com>
Gerrit-MessageType: newchange
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