Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49694 )
Change subject: cpu,arm: Add a method to RegClass-es to print register
values.
......................................................................
cpu,arm: Add a method to RegClass-es to print register values.
This further abstracts the properties of registers so they can be
removed from the CPUs.
Change-Id: I2aa1bffe8b095a0301579e60270965c611d6db4e
---
M src/arch/arm/isa.cc
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
3 files changed, 85 insertions(+), 26 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index acf5083..18359b0 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -75,7 +75,7 @@
}
} miscRegClassOps;
-VecElemRegClassOps vecRegElemClassOps(NumVecElemPerVecReg);
+VecElemRegClassOps<ArmISA::VecElem>
vecRegElemClassOps(NumVecElemPerVecReg);
ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
@@ -84,7 +84,7 @@
_regClasses.emplace_back(NUM_INTREGS, INTREG_ZERO);
_regClasses.emplace_back(0);
_regClasses.emplace_back(NumVecRegs, -1, sizeof(VecRegContainer));
- _regClasses.emplace_back(NumVecRegs * TheISA::NumVecElemPerVecReg,
+ _regClasses.emplace_back(NumVecRegs * ArmISA::NumVecElemPerVecReg,
vecRegElemClassOps);
_regClasses.emplace_back(NumVecPredRegs, -1,
sizeof(VecPredRegContainer));
_regClasses.emplace_back(NUM_CCREGS);
diff --git a/src/cpu/reg_class.cc b/src/cpu/reg_class.cc
index b667838..57a489a 100644
--- a/src/cpu/reg_class.cc
+++ b/src/cpu/reg_class.cc
@@ -39,23 +39,61 @@
*/
#include "cpu/reg_class.hh"
+
+#include <sstream>
+
#include "base/cprintf.hh"
namespace gem5
{
std::string
-DefaultRegClassOps::regName(const RegId &id) const
+RegClassOps::regName(const RegId &id) const
{
return csprintf("r%d", id.index());
}
std::string
-VecElemRegClassOps::regName(const RegId &id) const
+RegClassOps::valString(const void *val, size_t size) const
{
- RegIndex reg_idx = id.index() / elemsPerVec;
- RegIndex elem_idx = id.index() % elemsPerVec;
- return csprintf("v%d[%d]", reg_idx, elem_idx);
+ // If this is just a RegVal, or could be interpreted as one, print it
+ // that way.
+ if (size == sizeof(uint64_t))
+ return csprintf("%s", *(const uint64_t *)val);
+ else if (size == sizeof(uint32_t))
+ return csprintf("%s", *(const uint32_t *)val);
+ else if (size == sizeof(uint16_t))
+ return csprintf("%s", *(const uint16_t *)val);
+ else if (size == sizeof(uint8_t))
+ return csprintf("%s", *(const uint8_t *)val);
+
+ // Otherwise, print it as a sequence of bytes, 4 in a chunk, separated
by
+ // spaces, and all surrounded by []s.
+
+ std::stringstream out;
+ ccprintf(out, "[");
+
+ constexpr size_t chunk_size = 4;
+ const uint8_t *bytes = (const uint8_t *)val;
+
+ while (size >= chunk_size) {
+ size -= chunk_size;
+ if (size) {
+ ccprintf(out, "%2x%2x%2x%2x ", bytes[0], bytes[1], bytes[2],
+ bytes[3]);
+ } else {
+ ccprintf(out, "%2x%2x%2x%2x", bytes[0], bytes[1], bytes[2],
+ bytes[3]);
+ }
+ bytes += chunk_size;
+ }
+
+ while (size--)
+ ccprintf(out, "%2x", *bytes++);
+
+ ccprintf(out, "]");
+
+ return out.str();
}
const char *RegId::regClassStrings[] = {
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index aa37e8d..a405cf6 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -41,9 +41,11 @@
#ifndef __CPU__REG_CLASS_HH__
#define __CPU__REG_CLASS_HH__
+#include <any>
#include <cstddef>
#include <string>
+#include "base/cprintf.hh"
#include "base/intmath.hh"
#include "base/types.hh"
@@ -69,24 +71,8 @@
class RegClassOps
{
public:
- virtual std::string regName(const RegId &id) const = 0;
-};
-
-class DefaultRegClassOps : public RegClassOps
-{
- public:
- std::string regName(const RegId &id) const override;
-};
-
-class VecElemRegClassOps : public RegClassOps
-{
- protected:
- size_t elemsPerVec;
-
- public:
- VecElemRegClassOps(size_t elems_per_vec) : elemsPerVec(elems_per_vec)
{}
-
- std::string regName(const RegId &id) const override;
+ virtual std::string regName(const RegId &id) const;
+ virtual std::string valString(const void *val, size_t size) const;
};
class RegClass
@@ -100,7 +86,7 @@
// be calculated with a multiply.
size_t _regShift;
- static inline DefaultRegClassOps defaultOps;
+ static inline RegClassOps defaultOps;
RegClassOps *_ops = &defaultOps;
public:
@@ -122,6 +108,11 @@
size_t regShift() const { return _regShift; }
std::string regName(const RegId &id) const { return _ops->regName(id);
}
+ std::string
+ valString(const void *val) const
+ {
+ return _ops->valString(val, size());
+ }
};
/** Register ID: describe an architectural register with its class and
index.
@@ -195,6 +186,36 @@
}
};
+template <typename ValueType>
+class TypedRegClassOps : public RegClassOps
+{
+ public:
+ std::string
+ valString(const void *val, size_t size) const override
+ {
+ assert(size == sizeof(ValueType));
+ return csprintf("%s", *(const ValueType *)val);
+ }
+};
+
+template <typename ValueType>
+class VecElemRegClassOps : public TypedRegClassOps<ValueType>
+{
+ protected:
+ size_t elemsPerVec;
+
+ public:
+ VecElemRegClassOps(size_t elems_per_vec) : elemsPerVec(elems_per_vec)
{}
+
+ std::string
+ regName(const RegId &id) const override
+ {
+ RegIndex reg_idx = id.index() / elemsPerVec;
+ RegIndex elem_idx = id.index() % elemsPerVec;
+ return csprintf("v%d[%d]", reg_idx, elem_idx);
+ }
+};
+
/** Physical register ID.
* Like a register ID but physical. The inheritance is private because the
* only relationship between this types is functional, and it is done to
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2aa1bffe8b095a0301579e60270965c611d6db4e
Gerrit-Change-Number: 49694
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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