Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49701 )
Change subject: arm: Replace readVecPredReg with getReg in the tarmac
tracer.
......................................................................
arm: Replace readVecPredReg with getReg in the tarmac tracer.
Change-Id: Id290b4b63ca0cf9982327e1451d12917e9d99272
---
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_record_v8.cc
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index 55b27f3..3f1db63 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -786,8 +786,8 @@
break;
case REG_P:
{
- const ArmISA::VecPredRegContainer& pc =
- thread->readVecPredReg(RegId(VecPredRegClass,
it->index));
+ ArmISA::VecPredRegContainer pc;
+ thread->getReg(RegId(VecPredRegClass, it->index), &pc);
auto pv = pc.as<uint8_t>();
uint64_t p = 0;
for (int i = maxVectorLength * 8; i > 0; ) {
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc
b/src/arch/arm/tracers/tarmac_record_v8.cc
index 8dd96d1..f34a183 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -163,8 +163,8 @@
)
{
auto thread = tarmCtx.thread;
- const auto& pred_container = thread->readVecPredReg(
- RegId(regClass, regRelIdx));
+ ArmISA::VecPredRegContainer pred_container;
+ thread->getReg(RegId(regClass, regRelIdx), &pred_container);
// Predicate registers are always 1/8 the size of related vector
// registers. (getCurSveVecLenInBits(thread) / 8)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id290b4b63ca0cf9982327e1451d12917e9d99272
Gerrit-Change-Number: 49701
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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