Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49708 )
Change subject: cpu: Remove VecRegContainer from ThreadContext::compare.
......................................................................
cpu: Remove VecRegContainer from ThreadContext::compare.
Change-Id: I5a0f9d30fe56806d46fb54d62e1e58d02a319879
---
M src/cpu/thread_context.cc
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 2e0ed61..3e584ad 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -83,13 +83,19 @@
}
// Then loop through the vector registers.
- for (int i = 0; i < regClasses.at(VecRegClass).size(); ++i) {
+ const auto &vec_class = regClasses.at(VecRegClass);
+ std::vector<uint8_t> vec1(vec_class.regBytes());
+ std::vector<uint8_t> vec2(vec_class.regBytes());
+ for (int i = 0; i < vec_class.size(); ++i) {
RegId rid(VecRegClass, i);
- const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
- const TheISA::VecRegContainer& t2 = two->readVecReg(rid);
- if (t1 != t2)
+
+ one->getReg(rid, vec1.data());
+ two->getReg(rid, vec2.data());
+ if (vec1 != vec2) {
panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
- i, t1, t2);
+ i, vec_class.valString(vec1.data()),
+ vec_class.valString(vec2.data()));
+ }
}
// Then loop through the predicate registers.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5a0f9d30fe56806d46fb54d62e1e58d02a319879
Gerrit-Change-Number: 49708
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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