[gem5-dev] Change in gem5/gem5[develop]: arch: Introduce an intermediate RegOperand class in operand_types.py.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49719 )

Change subject: arch: Introduce an intermediate RegOperand class in  
operand_types.py.
......................................................................

arch: Introduce an intermediate RegOperand class in operand_types.py.

There are a number of operand types which are registers. Define a
RegOperand type which they can all inherit from to get register generic
functionality. This will also become a way to add generic register types
with malleable properties at the ISA level.

Change-Id: I01a1d5d133d8f64106d005a744631f64e6808e57
---
M src/arch/isa_parser/operand_types.py
1 file changed, 9 insertions(+), 24 deletions(-)



diff --git a/src/arch/isa_parser/operand_types.py  
b/src/arch/isa_parser/operand_types.py
index 66d755e..f93579b 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -170,13 +170,13 @@
         # to avoid 'uninitialized variable' errors from the compiler.
         return self.ctype + ' ' + self.base_name + ' = 0;\n';

-
-class IntRegOperand(Operand):
-    reg_class = 'IntRegClass'
-
+class RegOperand(Operand):
     def isReg(self):
         return 1

+class IntRegOperand(RegOperand):
+    reg_class = 'IntRegClass'
+
     def isIntReg(self):
         return 1

@@ -243,12 +243,9 @@

         return wb

-class FloatRegOperand(Operand):
+class FloatRegOperand(RegOperand):
     reg_class = 'FloatRegClass'

-    def isReg(self):
-        return 1
-
     def isFloatReg(self):
         return 1

@@ -306,16 +303,13 @@
         }''' % (self.ctype, self.base_name, wp)
         return wb

-class VecRegOperand(Operand):
+class VecRegOperand(RegOperand):
     reg_class = 'VecRegClass'

     def __init__(self, parser, full_name, ext, is_src, is_dest):
         Operand.__init__(self, parser, full_name, ext, is_src, is_dest)
         self.elemExt = None

-    def isReg(self):
-        return 1
-
     def isVecReg(self):
         return 1

@@ -453,12 +447,9 @@
         if self.is_dest:
             self.op_rd = self.makeReadW(predWrite) + self.op_rd

-class VecElemOperand(Operand):
+class VecElemOperand(RegOperand):
     reg_class = 'VecElemClass'

-    def isReg(self):
-        return 1
-
     def isVecElem(self):
         return 1

@@ -492,12 +483,9 @@
         return f'\n\txc->setRegOperand(this, {self.dest_reg_idx}, ' \
                f'&{self.base_name});'

-class VecPredRegOperand(Operand):
+class VecPredRegOperand(RegOperand):
     reg_class = 'VecPredRegClass'

-    def isReg(self):
-        return 1
-
     def isVecPredReg(self):
         return 1

@@ -572,12 +560,9 @@
         if self.is_dest:
             self.op_rd = self.makeReadW(predWrite) + self.op_rd

-class CCRegOperand(Operand):
+class CCRegOperand(RegOperand):
     reg_class = 'CCRegClass'

-    def isReg(self):
-        return 1
-
     def isCCReg(self):
         return 1


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I01a1d5d133d8f64106d005a744631f64e6808e57
Gerrit-Change-Number: 49719
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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