Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49722 )
Change subject: arch: Simplify the VecElemOperand class.
......................................................................
arch: Simplify the VecElemOperand class.
Oddly, makeDecl would conditionally declare the operand, but only
because makeRead would also declare it. Instead, make makeRead work like
normal, and get rid of the custom makeDecl.
Change-Id: I26c6f01f971778ad5075f8d3f49d9816f371f5b3
---
M src/arch/isa_parser/operand_types.py
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/src/arch/isa_parser/operand_types.py
b/src/arch/isa_parser/operand_types.py
index f67f27d..594b544 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -394,17 +394,9 @@
class VecElemOperand(RegOperand):
reg_class = 'VecElemClass'
- def makeDecl(self):
- if self.is_dest and not self.is_src:
- return '\n\t%s %s;' % (self.ctype, self.base_name)
- else:
- return ''
-
def makeRead(self, predRead):
- c_read = \
- f'xc->getRegOperand(this, {self.src_reg_idx},
&{self.base_name})'
-
- return f'\n\t{self.ctype} {self.base_name}; {c_read};\n'
+ return f'xc->getRegOperand(this, {self.src_reg_idx}, ' \
+ f'&{self.base_name});'
def makeWrite(self, predWrite):
return f'\n\txc->setRegOperand(this, {self.dest_reg_idx}, ' \
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I26c6f01f971778ad5075f8d3f49d9816f371f5b3
Gerrit-Change-Number: 49722
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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