Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49729 )
Change subject: arch-mips: Use the OperandDesc classes in the ISA
description.
......................................................................
arch-mips: Use the OperandDesc classes in the ISA description.
Change-Id: I79c1246a352125313841f1e3d674374352803af6
---
M src/arch/mips/isa/operands.isa
1 file changed, 75 insertions(+), 75 deletions(-)
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index 3cb2d43..2db0f7d 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -41,113 +41,113 @@
def operands {{
#General Purpose Integer Reg Operands
- 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
- 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
- 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
+ 'Rd': IntRegOp('uw', 'RD', 'IsInteger', 1),
+ 'Rs': IntRegOp('uw', 'RS', 'IsInteger', 2),
+ 'Rt': IntRegOp('uw', 'RT', 'IsInteger', 3),
#Immediate Value operand
- 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
+ 'IntImm': IntRegOp('uw', 'INTIMM', 'IsInteger', 3),
#Operands used for Link Insts
- 'R31': ('IntReg', 'uw','31','IsInteger', 4),
+ 'R31': IntRegOp('uw', '31', 'IsInteger', 4),
#Special Integer Reg operands
- 'LO0': ('IntReg', 'uw','INTREG_LO', 'IsInteger', 6),
- 'HI0': ('IntReg', 'uw','INTREG_HI', 'IsInteger', 7),
+ 'LO0': IntRegOp('uw', 'INTREG_LO', 'IsInteger', 6),
+ 'HI0': IntRegOp('uw', 'INTREG_HI', 'IsInteger', 7),
#Bitfield-dependent HI/LO Register Access
- 'LO_RD_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACDST*3', None, 6),
- 'HI_RD_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACDST*3', None, 7),
- 'LO_RS_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACSRC*3', None, 6),
- 'HI_RS_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACSRC*3', None, 7),
+ 'LO_RD_SEL': IntRegOp('uw', 'INTREG_DSP_LO0 + ACDST*3', None, 6),
+ 'HI_RD_SEL': IntRegOp('uw', 'INTREG_DSP_HI0 + ACDST*3', None, 7),
+ 'LO_RS_SEL': IntRegOp('uw', 'INTREG_DSP_LO0 + ACSRC*3', None, 6),
+ 'HI_RS_SEL': IntRegOp('uw', 'INTREG_DSP_HI0 + ACSRC*3', None, 7),
#DSP Special Purpose Integer Operands
- 'DSPControl': ('IntReg', 'uw', 'INTREG_DSP_CONTROL', None, 8),
- 'DSPLo0': ('IntReg', 'uw', 'INTREG_LO', None, 1),
- 'DSPHi0': ('IntReg', 'uw', 'INTREG_HI', None, 1),
- 'DSPACX0': ('IntReg', 'uw', 'INTREG_DSP_ACX0', None, 1),
- 'DSPLo1': ('IntReg', 'uw', 'INTREG_DSP_LO1', None, 1),
- 'DSPHi1': ('IntReg', 'uw', 'INTREG_DSP_HI1', None, 1),
- 'DSPACX1': ('IntReg', 'uw', 'INTREG_DSP_ACX1', None, 1),
- 'DSPLo2': ('IntReg', 'uw', 'INTREG_DSP_LO2', None, 1),
- 'DSPHi2': ('IntReg', 'uw', 'INTREG_DSP_HI2', None, 1),
- 'DSPACX2': ('IntReg', 'uw', 'INTREG_DSP_ACX2', None, 1),
- 'DSPLo3': ('IntReg', 'uw', 'INTREG_DSP_LO3', None, 1),
- 'DSPHi3': ('IntReg', 'uw', 'INTREG_DSP_HI3', None, 1),
- 'DSPACX3': ('IntReg', 'uw', 'INTREG_DSP_ACX3', None, 1),
+ 'DSPControl': IntRegOp('uw', 'INTREG_DSP_CONTROL', None, 8),
+ 'DSPLo0': IntRegOp('uw', 'INTREG_LO', None, 1),
+ 'DSPHi0': IntRegOp('uw', 'INTREG_HI', None, 1),
+ 'DSPACX0': IntRegOp('uw', 'INTREG_DSP_ACX0', None, 1),
+ 'DSPLo1': IntRegOp('uw', 'INTREG_DSP_LO1', None, 1),
+ 'DSPHi1': IntRegOp('uw', 'INTREG_DSP_HI1', None, 1),
+ 'DSPACX1': IntRegOp('uw', 'INTREG_DSP_ACX1', None, 1),
+ 'DSPLo2': IntRegOp('uw', 'INTREG_DSP_LO2', None, 1),
+ 'DSPHi2': IntRegOp('uw', 'INTREG_DSP_HI2', None, 1),
+ 'DSPACX2': IntRegOp('uw', 'INTREG_DSP_ACX2', None, 1),
+ 'DSPLo3': IntRegOp('uw', 'INTREG_DSP_LO3', None, 1),
+ 'DSPHi3': IntRegOp('uw', 'INTREG_DSP_HI3', None, 1),
+ 'DSPACX3': IntRegOp('uw', 'INTREG_DSP_ACX3', None, 1),
#Floating Point Reg Operands
- 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
- 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
- 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
- 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
+ 'Fd': FloatRegOp('sf', 'FD', 'IsFloating', 1),
+ 'Fs': FloatRegOp('sf', 'FS', 'IsFloating', 2),
+ 'Ft': FloatRegOp('sf', 'FT', 'IsFloating', 3),
+ 'Fr': FloatRegOp('sf', 'FR', 'IsFloating', 3),
#Special Purpose Floating Point Control Reg Operands
- 'FIR': ('FloatReg', 'uw', 'FLOATREG_FIR', 'IsFloating', 1),
- 'FCCR': ('FloatReg', 'uw', 'FLOATREG_FCCR', 'IsFloating', 2),
- 'FEXR': ('FloatReg', 'uw', 'FLOATREG_FEXR', 'IsFloating', 3),
- 'FENR': ('FloatReg', 'uw', 'FLOATREG_FENR', 'IsFloating', 3),
- 'FCSR': ('FloatReg', 'uw', 'FLOATREG_FCSR', 'IsFloating', 3),
+ 'FIR': FloatRegOp('uw', 'FLOATREG_FIR', 'IsFloating', 1),
+ 'FCCR': FloatRegOp('uw', 'FLOATREG_FCCR', 'IsFloating', 2),
+ 'FEXR': FloatRegOp('uw', 'FLOATREG_FEXR', 'IsFloating', 3),
+ 'FENR': FloatRegOp('uw', 'FLOATREG_FENR', 'IsFloating', 3),
+ 'FCSR': FloatRegOp('uw', 'FLOATREG_FCSR', 'IsFloating', 3),
#Operands For Paired Singles FP Operations
- 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
- 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
- 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
- 'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
- 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
- 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
- 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
- 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
+ 'Fd1': FloatRegOp('sf', 'FD', 'IsFloating', 4),
+ 'Fd2': FloatRegOp('sf', 'FD+1', 'IsFloating', 4),
+ 'Fs1': FloatRegOp('sf', 'FS', 'IsFloating', 5),
+ 'Fs2': FloatRegOp('sf', 'FS+1', 'IsFloating', 5),
+ 'Ft1': FloatRegOp('sf', 'FT', 'IsFloating', 6),
+ 'Ft2': FloatRegOp('sf', 'FT+1', 'IsFloating', 6),
+ 'Fr1': FloatRegOp('sf', 'FR', 'IsFloating', 7),
+ 'Fr2': FloatRegOp('sf', 'FR+1', 'IsFloating', 7),
#Status Control Reg
- 'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1),
+ 'Status': ControlRegOp('uw', 'MISCREG_STATUS', None, 1),
#LL Flag
- 'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
+ 'LLFlag': ControlRegOp('uw', 'MISCREG_LLFLAG', None, 1),
#Thread pointer value for SE mode
- 'TpValue': ('ControlReg', 'ud', 'MISCREG_TP_VALUE', None, 1),
+ 'TpValue': ControlRegOp('ud', 'MISCREG_TP_VALUE', None, 1),
# Index Register
- 'Index': ('ControlReg','uw','MISCREG_INDEX',None,1),
+ 'Index': ControlRegOp('uw','MISCREG_INDEX',None,1),
- 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
+ 'CP0_RD_SEL': ControlRegOp('uw', '(RD << 3 | SEL)', None, 1),
#MT Control Regs
- 'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1),
- 'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1),
- 'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1),
- 'TCStatus': ('ControlReg', 'uw', 'MISCREG_TC_STATUS', None, 1),
- 'TCRestart': ('ControlReg', 'uw', 'MISCREG_TC_RESTART', None, 1),
- 'VPEConf0': ('ControlReg', 'uw', 'MISCREG_VPE_CONF0', None, 1),
- 'VPEControl': ('ControlReg', 'uw', 'MISCREG_VPE_CONTROL', None, 1),
- 'YQMask': ('ControlReg', 'uw', 'MISCREG_YQMASK', None, 1),
+ 'MVPConf0': ControlRegOp('uw', 'MISCREG_MVP_CONF0', None, 1),
+ 'MVPControl': ControlRegOp('uw', 'MISCREG_MVP_CONTROL', None, 1),
+ 'TCBind': ControlRegOp('uw', 'MISCREG_TC_BIND', None, 1),
+ 'TCStatus': ControlRegOp('uw', 'MISCREG_TC_STATUS', None, 1),
+ 'TCRestart': ControlRegOp('uw', 'MISCREG_TC_RESTART', None, 1),
+ 'VPEConf0': ControlRegOp('uw', 'MISCREG_VPE_CONF0', None, 1),
+ 'VPEControl': ControlRegOp('uw', 'MISCREG_VPE_CONTROL', None, 1),
+ 'YQMask': ControlRegOp('uw', 'MISCREG_YQMASK', None, 1),
#CP0 Control Regs
- 'EntryHi': ('ControlReg','uw', 'MISCREG_ENTRYHI',None,1),
- 'EntryLo0': ('ControlReg','uw', 'MISCREG_ENTRYLO0',None,1),
- 'EntryLo1': ('ControlReg','uw', 'MISCREG_ENTRYLO1',None,1),
- 'PageMask': ('ControlReg','uw', 'MISCREG_PAGEMASK',None,1),
- 'Random': ('ControlReg','uw', 'MISCREG_CP0_RANDOM',None,1),
- 'ErrorEPC': ('ControlReg','uw', 'MISCREG_ERROR_EPC',None,1),
- 'EPC': ('ControlReg','uw', 'MISCREG_EPC',None,1),
- 'DEPC': ('ControlReg','uw', 'MISCREG_DEPC',None,1),
- 'IntCtl': ('ControlReg','uw', 'MISCREG_INTCTL',None,1),
- 'SRSCtl': ('ControlReg','uw', 'MISCREG_SRSCTL',None,1),
- 'Config': ('ControlReg','uw', 'MISCREG_CONFIG',None,1),
- 'Config3': ('ControlReg','uw', 'MISCREG_CONFIG3',None,1),
- 'Config1': ('ControlReg','uw', 'MISCREG_CONFIG1',None,1),
- 'Config2': ('ControlReg','uw', 'MISCREG_CONFIG2',None,1),
- 'PageGrain': ('ControlReg','uw', 'MISCREG_PAGEGRAIN',None,1),
- 'Debug': ('ControlReg','uw', 'MISCREG_DEBUG',None,1),
- 'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1),
+ 'EntryHi': ControlRegOp('uw', 'MISCREG_ENTRYHI',None,1),
+ 'EntryLo0': ControlRegOp('uw', 'MISCREG_ENTRYLO0',None,1),
+ 'EntryLo1': ControlRegOp('uw', 'MISCREG_ENTRYLO1',None,1),
+ 'PageMask': ControlRegOp('uw', 'MISCREG_PAGEMASK',None,1),
+ 'Random': ControlRegOp('uw', 'MISCREG_CP0_RANDOM',None,1),
+ 'ErrorEPC': ControlRegOp('uw', 'MISCREG_ERROR_EPC',None,1),
+ 'EPC': ControlRegOp('uw', 'MISCREG_EPC',None,1),
+ 'DEPC': ControlRegOp('uw', 'MISCREG_DEPC',None,1),
+ 'IntCtl': ControlRegOp('uw', 'MISCREG_INTCTL',None,1),
+ 'SRSCtl': ControlRegOp('uw', 'MISCREG_SRSCTL',None,1),
+ 'Config': ControlRegOp('uw', 'MISCREG_CONFIG',None,1),
+ 'Config3': ControlRegOp('uw', 'MISCREG_CONFIG3',None,1),
+ 'Config1': ControlRegOp('uw', 'MISCREG_CONFIG1',None,1),
+ 'Config2': ControlRegOp('uw', 'MISCREG_CONFIG2',None,1),
+ 'PageGrain': ControlRegOp('uw', 'MISCREG_PAGEGRAIN',None,1),
+ 'Debug': ControlRegOp('uw', 'MISCREG_DEBUG',None,1),
+ 'Cause': ControlRegOp('uw', 'MISCREG_CAUSE',None,1),
#Memory Operand
- 'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), 4),
+ 'Mem': MemOp('uw', None, (None, 'IsLoad', 'IsStore'), 4),
#Program Counter Operands
- 'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 4),
- 'NPC': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 4),
- 'NNPC': ('PCState', 'uw', 'nnpc', (None, None, 'IsControl'), 4)
+ 'PC': PCStateOp('uw', 'pc', (None, None, 'IsControl'), 4),
+ 'NPC': PCStateOp('uw', 'npc', (None, None, 'IsControl'), 4),
+ 'NNPC': PCStateOp('uw', 'nnpc', (None, None, 'IsControl'), 4)
}};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I79c1246a352125313841f1e3d674374352803af6
Gerrit-Change-Number: 49729
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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