Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49735 )
Change subject: arch: Update the default "func" value in the ISA parser.
......................................................................
arch: Update the default "func" value in the ISA parser.
Now that there is a unified (get|set)RegOperand accessor for all
register based operands, that can be used as a reasonable default in the
ISA parser code.
Change-Id: Icef62aa6c16fb8b929ee0fa0d60b23553e0bf515
---
M src/arch/isa_parser/operand_types.py
1 file changed, 14 insertions(+), 17 deletions(-)
diff --git a/src/arch/isa_parser/operand_types.py
b/src/arch/isa_parser/operand_types.py
index 4ba3b4f..90b463d 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -103,7 +103,7 @@
src_reg_constructor = '\n\tsetSrcRegIdx(_numSrcRegs++, RegId(%s, %s));'
dst_reg_constructor = '\n\tsetDestRegIdx(_numDestRegs++,
RegId(%s, %s));'
- def buildReadCode(self, predRead, func=None):
+ def buildReadCode(self, predRead, func='getRegOperand'):
subst_dict = {"name": self.base_name,
"func": func,
"reg_idx": self.reg_spec,
@@ -114,7 +114,7 @@
code = self.read_code % subst_dict
return '%s = %s;\n' % (self.base_name, code)
- def buildWriteCode(self, predWrite, func=None):
+ def buildWriteCode(self, predWrite, func='setRegOperand'):
subst_dict = {"name": self.base_name,
"func": func,
"reg_idx": self.reg_spec,
@@ -231,7 +231,7 @@
class RegOperand(BaseRegOperand):
def makeRead(self, predRead):
if self.read_code != None:
- return self.buildReadCode(predRead, 'getRegOperand')
+ return self.buildReadCode(predRead)
if predRead:
rindex = '_sourceIndex++'
@@ -251,7 +251,7 @@
def makeWrite(self, predWrite):
if self.write_code != None:
- return self.buildWriteCode(predWrite, 'setRegOperand')
+ return self.buildWriteCode(predWrite)
reg_val = self.base_name
@@ -356,7 +356,7 @@
c_readw = f'\t\tauto &tmp_d{rindex} = \n' \
f'\t\t *({self.parser.namespace}::VecRegContainer
*)\n' \
- f'\t\t xc->{func}(this, {rindex});\n'
+ f'\t\t xc->getWritableRegOperand(this, {rindex});\n'
if self.elemExt:
c_readw += '\t\tauto %s = tmp_d%s.as<%s>();\n' %
(self.base_name,
rindex, self.parser.operandTypeMap[self.elemExt])
@@ -384,9 +384,8 @@
return c_read
def makeRead(self, predRead):
- func = 'getRegOperand'
if self.read_code != None:
- return self.buildReadCode(predRead, func)
+ return self.buildReadCode(predRead)
if predRead:
rindex = '_sourceIndex++'
@@ -399,7 +398,7 @@
c_read = f'\t\t{self.parser.namespace}::VecRegContainer ' \
f'\t\t tmp_s{rindex};\n' \
- f'\t\txc->{func}(this, {rindex}, &tmp_s{rindex});\n'
+ f'\t\txc->getRegOperand(this, {rindex},
&tmp_s{rindex});\n'
# If the parser has detected that elements are being access, create
# the appropriate view
if self.elemExt:
@@ -415,9 +414,8 @@
return c_read
def makeWrite(self, predWrite):
- func = 'setRegOperand'
if self.write_code != None:
- return self.buildWriteCode(predWrite, func)
+ return self.buildWriteCode(predWrite)
wb = '''
if (traceData) {
@@ -443,9 +441,8 @@
return ''
def makeRead(self, predRead):
- func = 'getRegOperand'
if self.read_code != None:
- return self.buildReadCode(predRead, func)
+ return self.buildReadCode(predRead)
if predRead:
rindex = '_sourceIndex++'
@@ -454,7 +451,7 @@
c_read = f'\t\t{self.parser.namespace}::VecPredRegContainer ' \
f'\t\t tmp_s{rindex}; ' \
- f'xc->{func}(this, {rindex}, &tmp_s{rindex});\n'
+ f'xc->getRegOperand(this, {rindex}, &tmp_s{rindex});\n'
if self.ext:
c_read += f'\t\tauto {self.base_name} = ' \
f'tmp_s{rindex}.as<' \
@@ -464,7 +461,7 @@
def makeReadW(self, predWrite):
func = 'getWritableRegOperand'
if self.read_code != None:
- return self.buildReadCode(predWrite, func)
+ return self.buildReadCode(predWrite, 'getWritableRegOperand')
if predWrite:
rindex = '_destIndex++'
@@ -473,7 +470,8 @@
c_readw = f'\t\tauto &tmp_d{rindex} = \n' \
f'\t\t *({self.parser.namespace}::' \
- f'VecPredRegContainer *)xc->{func}(this, {rindex});\n'
+ f'VecPredRegContainer *)xc->getWritableRegOperand(' \
+ f'this, {rindex});\n'
if self.ext:
c_readw += '\t\tauto %s = tmp_d%s.as<%s>();\n' % (
self.base_name, rindex,
@@ -481,9 +479,8 @@
return c_readw
def makeWrite(self, predWrite):
- func = 'setRegOperand'
if self.write_code != None:
- return self.buildWriteCode(predWrite, func)
+ return self.buildWriteCode(predWrite)
wb = '''
if (traceData) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icef62aa6c16fb8b929ee0fa0d60b23553e0bf515
Gerrit-Change-Number: 49735
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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