Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49744 )
Change subject: cpu: Treat the InvalidRegClass like the zero register.
......................................................................
cpu: Treat the InvalidRegClass like the zero register.
This is a transitional step towards the InvalidRegClass taking over for
the zero register.
Change-Id: I423e1f6b5138d8bb41493f9febb3b28f333f9f00
---
M src/cpu/checker/cpu_impl.hh
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/exec_context.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/probe/elastic_trace.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.cc
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/scoreboard.hh
M src/cpu/reg_class.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
13 files changed, 56 insertions(+), 22 deletions(-)
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 9d5c260..3ccd176 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -585,6 +585,8 @@
if (start_idx >= 0) {
const RegId& idx = inst->destRegIdx(start_idx);
switch (idx.classValue()) {
+ case InvalidRegClass:
+ break;
case IntRegClass:
thread->setIntReg(idx.index(), mismatch_val.as<RegVal>());
break;
@@ -613,6 +615,8 @@
const RegId& idx = inst->destRegIdx(i);
res = inst->popResult();
switch (idx.classValue()) {
+ case InvalidRegClass:
+ break;
case IntRegClass:
thread->setIntReg(idx.index(), res.as<RegVal>());
break;
diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc
index 534d1ab..b3fed0f 100644
--- a/src/cpu/minor/dyn_inst.cc
+++ b/src/cpu/minor/dyn_inst.cc
@@ -144,6 +144,9 @@
{
const auto ®_class = reg_classes.at(reg.classValue());
switch (reg.classValue()) {
+ case InvalidRegClass:
+ os << 'z';
+ break;
case MiscRegClass:
{
RegIndex misc_reg = reg.index();
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 9790444..3f022fb 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -147,7 +147,10 @@
RegVal
getRegOperand(const StaticInst *si, int idx) override
{
- return thread.getReg(si->srcRegIdx(idx));
+ const RegId ® = si->srcRegIdx(idx);
+ if (reg.is(InvalidRegClass))
+ return 0;
+ return thread.getReg(reg);
}
void
@@ -165,6 +168,9 @@
void
setRegOperand(const StaticInst *si, int idx, RegVal val) override
{
+ const RegId ® = si->destRegIdx(idx);
+ if (reg.is(InvalidRegClass))
+ return;
thread.setReg(si->destRegIdx(idx), val);
}
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 4daa2dd..23b5910 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -1185,7 +1185,10 @@
RegVal
getRegOperand(const StaticInst *si, int idx) override
{
- return cpu->getReg(regs.renamedSrcIdx(idx));
+ const PhysRegIdPtr reg = regs.renamedSrcIdx(idx);
+ if (reg->is(InvalidRegClass))
+ return 0;
+ return cpu->getReg(reg);
}
void
@@ -1206,7 +1209,10 @@
void
setRegOperand(const StaticInst *si, int idx, RegVal val) override
{
- cpu->setReg(regs.renamedDestIdx(idx), val);
+ const PhysRegIdPtr reg = regs.renamedDestIdx(idx);
+ if (reg->is(InvalidRegClass))
+ return;
+ cpu->setReg(reg, val);
setResult(val);
}
diff --git a/src/cpu/o3/probe/elastic_trace.cc
b/src/cpu/o3/probe/elastic_trace.cc
index 95baa59..422f69a 100644
--- a/src/cpu/o3/probe/elastic_trace.cc
+++ b/src/cpu/o3/probe/elastic_trace.cc
@@ -252,7 +252,8 @@
const RegId& src_reg = dyn_inst->srcRegIdx(src_idx);
if (!src_reg.is(MiscRegClass) &&
- !(src_reg.is(IntRegClass) && src_reg.index() == zeroReg)) {
+ !((src_reg.is(IntRegClass) && src_reg.index() == zeroReg) |
|
+ src_reg.is(InvalidRegClass))) {
// Get the physical register index of the i'th source register.
PhysRegIdPtr phys_src_reg =
dyn_inst->regs.renamedSrcIdx(src_idx);
DPRINTFR(ElasticTrace, "[sn:%lli] Check map for src reg"
@@ -284,7 +285,8 @@
// CC register and not a Misc register.
const RegId& dest_reg = dyn_inst->destRegIdx(dest_idx);
if (!dest_reg.is(MiscRegClass) &&
- !(dest_reg.is(IntRegClass) && dest_reg.index() ==
zeroReg)) {
+ !((dest_reg.is(IntRegClass) && dest_reg.index() ==
zeroReg) ||
+ dest_reg.is(InvalidRegClass))) {
// Get the physical register index of the i'th destination
// register.
PhysRegIdPtr phys_dest_reg =
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 4166a61..f402c23 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -313,6 +313,8 @@
const RegIndex idx = phys_reg->index();
switch (type) {
+ case InvalidRegClass:
+ break;
case IntRegClass:
if (phys_reg->index() != zeroReg.index())
intRegFile.reg(idx) = val;
diff --git a/src/cpu/o3/rename.cc b/src/cpu/o3/rename.cc
index cd58d31..3f3afec 100644
--- a/src/cpu/o3/rename.cc
+++ b/src/cpu/o3/rename.cc
@@ -1016,6 +1016,8 @@
renamed_reg = map->lookup(tc->flattenRegId(src_reg));
switch (src_reg.classValue()) {
+ case InvalidRegClass:
+ break;
case IntRegClass:
stats.intLookups++;
break;
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index 9ee0810..4219e72 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -82,6 +82,9 @@
if (arch_reg == zeroReg) {
assert(prev_reg->index() == zeroReg.index());
renamed_reg = prev_reg;
+ } else if (arch_reg.is(InvalidRegClass)) {
+ assert(prev_reg->is(InvalidRegClass));
+ renamed_reg = prev_reg;
} else if (prev_reg->getNumPinnedWrites() > 0) {
// Do not rename if the register is pinned
assert(arch_reg.getNumPinnedWrites() == 0); // Prevent pinning the
diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh
index 171a13e..32af51d 100644
--- a/src/cpu/o3/rename_map.hh
+++ b/src/cpu/o3/rename_map.hh
@@ -178,6 +178,8 @@
private:
std::array<SimpleRenameMap, CCRegClass + 1> renameMaps;
+ static inline PhysRegId invalidPhysRegId{};
+
/**
* The register file object is used only to get PhysRegIdPtr
* on MiscRegs, as they are stored in it.
@@ -209,8 +211,7 @@
RenameInfo
rename(const RegId& arch_reg)
{
- auto reg_class = arch_reg.classValue();
- if (reg_class == MiscRegClass) {
+ if (!arch_reg.isRenameable()) {
// misc regs aren't really renamed, just remapped
PhysRegIdPtr phys_reg = lookup(arch_reg);
// Set the new register to the previous one to keep the same
@@ -218,7 +219,7 @@
return RenameInfo(phys_reg, phys_reg);
}
- return renameMaps[reg_class].rename(arch_reg);
+ return renameMaps[arch_reg.classValue()].rename(arch_reg);
}
/**
@@ -232,7 +233,9 @@
lookup(const RegId& arch_reg) const
{
auto reg_class = arch_reg.classValue();
- if (reg_class == MiscRegClass) {
+ if (reg_class == InvalidRegClass) {
+ return &invalidPhysRegId;
+ } else if (reg_class == MiscRegClass) {
// misc regs aren't really renamed, they keep the same
// mapping throughout the execution.
return regFile->getMiscRegId(arch_reg.index());
@@ -252,8 +255,7 @@
setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
{
assert(phys_reg->is(arch_reg.classValue()));
- auto reg_class = arch_reg.classValue();
- if (reg_class == MiscRegClass) {
+ if (!arch_reg.isRenameable()) {
// Misc registers do not actually rename, so don't change
// their mappings. We end up here when a commit or squash
// tries to update or undo a hardwired misc reg nmapping,
@@ -262,7 +264,7 @@
return;
}
- return renameMaps[reg_class].setEntry(arch_reg, phys_reg);
+ return renameMaps[arch_reg.classValue()].setEntry(arch_reg,
phys_reg);
}
/**
diff --git a/src/cpu/o3/scoreboard.hh b/src/cpu/o3/scoreboard.hh
index 7a6b656..f02e53d 100644
--- a/src/cpu/o3/scoreboard.hh
+++ b/src/cpu/o3/scoreboard.hh
@@ -85,33 +85,33 @@
bool
getReg(PhysRegIdPtr phys_reg) const
{
- assert(phys_reg->flatIndex() < numPhysRegs);
-
if (phys_reg->isFixedMapping()) {
// Fixed mapping regs are always ready
return true;
}
+ assert(phys_reg->flatIndex() < numPhysRegs);
+
bool ready = regScoreBoard[phys_reg->flatIndex()];
if (phys_reg->is(IntRegClass) && phys_reg->index() == zeroReg)
assert(ready);
- return ready;
+ return regScoreBoard[phys_reg->flatIndex()];
}
/** Sets the register as ready. */
void
setReg(PhysRegIdPtr phys_reg)
{
- assert(phys_reg->flatIndex() < numPhysRegs);
-
if (phys_reg->isFixedMapping()) {
// Fixed mapping regs are always ready, ignore attempts to
change
// that
return;
}
+ assert(phys_reg->flatIndex() < numPhysRegs);
+
DPRINTF(Scoreboard, "Setting reg %i (%s) as ready\n",
phys_reg->index(), phys_reg->className());
@@ -122,14 +122,14 @@
void
unsetReg(PhysRegIdPtr phys_reg)
{
- assert(phys_reg->flatIndex() < numPhysRegs);
-
if (phys_reg->isFixedMapping()) {
// Fixed mapping regs are always ready, ignore attempts to
// change that
return;
}
+ assert(phys_reg->flatIndex() < numPhysRegs);
+
// zero reg should never be marked unready
if (phys_reg->is(IntRegClass) && phys_reg->index() == zeroReg)
return;
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 326b355..02ed4d8 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -167,7 +167,7 @@
bool
isRenameable() const
{
- return regClass != MiscRegClass;
+ return regClass != MiscRegClass && regClass != InvalidRegClass;
}
/** @return true if it is of the specified class. */
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index be32af1..f810292 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -311,6 +311,8 @@
getRegOperand(const StaticInst *si, int idx) override
{
const RegId ® = si->srcRegIdx(idx);
+ if (reg.is(InvalidRegClass))
+ return 0;
(*execContextStats.numRegReads[reg.classValue()])++;
return thread->getReg(reg);
}
@@ -335,6 +337,8 @@
setRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId ® = si->destRegIdx(idx);
+ if (reg.is(InvalidRegClass))
+ return;
(*execContextStats.numRegWrites[reg.classValue()])++;
thread->setReg(reg, val);
}
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 678a489..cee6ada 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -472,7 +472,7 @@
auto ®_file = regFiles[reg.classValue()];
const auto ®_class = reg_file.regClass;
- if (reg.index() == reg_class.zeroReg())
+ if (reg.index() == reg_class.zeroReg() || reg.is(InvalidRegClass))
return;
DPRINTFV(reg_class.debug(), "Setting %s register %s (%d)
to %#x.\n",
@@ -488,7 +488,7 @@
auto ®_file = regFiles[reg.classValue()];
const auto ®_class = reg_file.regClass;
- if (reg.index() == reg_class.zeroReg())
+ if (reg.index() == reg_class.zeroReg() || reg.is(InvalidRegClass))
return;
DPRINTFV(reg_class.debug(), "Setting %s register %d to %#x.\n",
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49744
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I423e1f6b5138d8bb41493f9febb3b28f333f9f00
Gerrit-Change-Number: 49744
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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