Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49756 )
Change subject: arch-x86: Convert segment indices to fit the style guide.
......................................................................
arch-x86: Convert segment indices to fit the style guide.
Capitalize only their first letter, and use a namespace to namespace
them instead of a SEGMENT_REG_ prefix.
Change-Id: I69778c8d052ad6cc0ffd9e74dd1c643e9d28048d
---
M src/arch/x86/emulenv.cc
M src/arch/x86/emulenv.hh
M src/arch/x86/faults.cc
M src/arch/x86/fs_workload.cc
M src/arch/x86/fs_workload.hh
M src/arch/x86/insts/microop_args.hh
M src/arch/x86/insts/static_inst.cc
M src/arch/x86/isa/macroop.isa
M src/arch/x86/isa/microasm.isa
M src/arch/x86/isa/operands.isa
M src/arch/x86/isa/specialize.isa
M src/arch/x86/process.cc
M src/arch/x86/regs/misc.hh
M src/arch/x86/regs/segment.hh
M src/arch/x86/tlb.cc
15 files changed, 96 insertions(+), 92 deletions(-)
diff --git a/src/arch/x86/emulenv.cc b/src/arch/x86/emulenv.cc
index 9ea3fba..f81b4d2 100644
--- a/src/arch/x86/emulenv.cc
+++ b/src/arch/x86/emulenv.cc
@@ -106,23 +106,23 @@
//the presence of a displacement is supposed to make the instruction
//default to the data segment.
if ((base != int_reg::Rbp && base != int_reg::Rsp) ||
machInst.dispSize) {
- seg = SEGMENT_REG_DS;
+ seg = segment_idx::Ds;
//Handle any segment override that might have been in the
instruction
int segFromInst = machInst.legacy.seg;
if (segFromInst)
- seg = (SegmentRegIndex)(segFromInst - 1);
+ seg = segFromInst - 1;
} else {
- seg = SEGMENT_REG_SS;
+ seg = segment_idx::Ss;
}
}
void EmulEnv::setSeg(const ExtMachInst & machInst)
{
- seg = SEGMENT_REG_DS;
+ seg = segment_idx::Ds;
//Handle any segment override that might have been in the instruction
int segFromInst = machInst.legacy.seg;
if (segFromInst)
- seg = (SegmentRegIndex)(segFromInst - 1);
+ seg = segFromInst - 1;
}
} // namespace gem5
diff --git a/src/arch/x86/emulenv.hh b/src/arch/x86/emulenv.hh
index f62d8f0..366ffe5 100644
--- a/src/arch/x86/emulenv.hh
+++ b/src/arch/x86/emulenv.hh
@@ -51,7 +51,7 @@
{
RegIndex reg;
RegIndex regm;
- SegmentRegIndex seg;
+ int seg;
uint8_t scale;
RegId index;
RegId base;
@@ -61,7 +61,7 @@
EmulEnv(RegIndex _reg, RegIndex _regm,
int _dataSize, int _addressSize, int _stackSize) :
- reg(_reg), regm(_regm), seg(SEGMENT_REG_DS),
+ reg(_reg), regm(_regm), seg(segment_idx::Ds),
scale(0), index(int_reg::T0),
base(int_reg::T0),
dataSize(_dataSize), addressSize(_addressSize),
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index e34004e..a082225 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -220,7 +220,7 @@
dataAttr.expandDown = 0;
dataAttr.system = 1;
- for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
+ for (int seg = 0; seg != segment_idx::NumIdxs; seg++) {
tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
diff --git a/src/arch/x86/fs_workload.cc b/src/arch/x86/fs_workload.cc
index dd71222..2914909 100644
--- a/src/arch/x86/fs_workload.cc
+++ b/src/arch/x86/fs_workload.cc
@@ -62,13 +62,12 @@
{}
void
-installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
- SegDescriptor desc, bool longmode)
+installSegDesc(ThreadContext *tc, int seg, SegDescriptor desc, bool
longmode)
{
- bool honorBase = !longmode || seg == SEGMENT_REG_FS ||
- seg == SEGMENT_REG_GS ||
- seg == SEGMENT_REG_TSL ||
- seg == SYS_SEGMENT_REG_TR;
+ bool honorBase = !longmode || seg == segment_idx::Fs ||
+ seg == segment_idx::Gs ||
+ seg == segment_idx::Tsl ||
+ seg == segment_idx::Tr;
SegAttr attr = 0;
@@ -233,7 +232,7 @@
tss.si = numGDTEntries - 1;
tc->setMiscReg(MISCREG_TR, (RegVal)tss);
- installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true);
+ installSegDesc(tc, segment_idx::Tr, tssDesc, true);
/*
* Identity map the first 4GB of memory. In order to map this region
@@ -309,12 +308,12 @@
tc->setMiscReg(MISCREG_EFER, efer);
// Start using longmode segments.
- installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
- installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
- installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
- installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
- installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
- installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
+ installSegDesc(tc, segment_idx::Cs, csDesc, true);
+ installSegDesc(tc, segment_idx::Ds, dsDesc, true);
+ installSegDesc(tc, segment_idx::Es, dsDesc, true);
+ installSegDesc(tc, segment_idx::Fs, dsDesc, true);
+ installSegDesc(tc, segment_idx::Gs, dsDesc, true);
+ installSegDesc(tc, segment_idx::Ss, dsDesc, true);
// Activate long mode.
cr0.pg = 1;
diff --git a/src/arch/x86/fs_workload.hh b/src/arch/x86/fs_workload.hh
index 6c2038f..1a4d204 100644
--- a/src/arch/x86/fs_workload.hh
+++ b/src/arch/x86/fs_workload.hh
@@ -72,8 +72,8 @@
} // namespace intelmp
-void installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
- SegDescriptor desc, bool longmode);
+void installSegDesc(ThreadContext *tc, int seg, SegDescriptor desc,
+ bool longmode);
class FsWorkload : public KernelWorkload
{
diff --git a/src/arch/x86/insts/microop_args.hh
b/src/arch/x86/insts/microop_args.hh
index e0c3f2b..81ed412 100644
--- a/src/arch/x86/insts/microop_args.hh
+++ b/src/arch/x86/insts/microop_args.hh
@@ -366,7 +366,7 @@
disp(args.disp), segment(args.segment.index),
size(inst->addressSize)
{
- assert(segment < NUM_SEGMENTREGS);
+ assert(segment < segment_idx::NumIdxs);
}
void
diff --git a/src/arch/x86/insts/static_inst.cc
b/src/arch/x86/insts/static_inst.cc
index 0b1a000..03d844b 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -64,43 +64,43 @@
{
switch (segment)
{
- case SEGMENT_REG_ES:
+ case segment_idx::Es:
ccprintf(os, "ES");
break;
- case SEGMENT_REG_CS:
+ case segment_idx::Cs:
ccprintf(os, "CS");
break;
- case SEGMENT_REG_SS:
+ case segment_idx::Ss:
ccprintf(os, "SS");
break;
- case SEGMENT_REG_DS:
+ case segment_idx::Ds:
ccprintf(os, "DS");
break;
- case SEGMENT_REG_FS:
+ case segment_idx::Fs:
ccprintf(os, "FS");
break;
- case SEGMENT_REG_GS:
+ case segment_idx::Gs:
ccprintf(os, "GS");
break;
- case SEGMENT_REG_HS:
+ case segment_idx::Hs:
ccprintf(os, "HS");
break;
- case SEGMENT_REG_TSL:
+ case segment_idx::Tsl:
ccprintf(os, "TSL");
break;
- case SEGMENT_REG_TSG:
+ case segment_idx::Tsg:
ccprintf(os, "TSG");
break;
- case SEGMENT_REG_LS:
+ case segment_idx::Ls:
ccprintf(os, "LS");
break;
- case SEGMENT_REG_MS:
+ case segment_idx::Ms:
ccprintf(os, "MS");
break;
- case SYS_SEGMENT_REG_TR:
+ case segment_idx::Tr:
ccprintf(os, "TR");
break;
- case SYS_SEGMENT_REG_IDTR:
+ case segment_idx::Idtr:
ccprintf(os, "IDTR");
break;
default:
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index 9150fe9..69e2d1d 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -279,7 +279,7 @@
self.regUsed = False
self.regm = "0"
self.regmUsed = False
- self.seg = "SEGMENT_REG_DS"
+ self.seg = "segment_idx::Ds"
self.size = None
self.addressSize = "ADDRSIZE"
self.dataSize = "OPSIZE"
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 549a4b1..6c814de 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -83,9 +83,9 @@
assembler.symbols["ufp%d" % num] = \
fpRegIdx("FLOATREG_MICROFP(%d)" % num)
# Add in symbols for the segment descriptor registers
- for letter in ("C", "D", "E", "F", "G", "H", "S"):
+ for letter in ("c", "d", "e", "f", "g", "h", "s"):
assembler.symbols["%ss" % letter.lower()] = \
- segRegIdx("SEGMENT_REG_%sS" % letter)
+ segRegIdx(f"segment_idx::{letter.capitalize()}s")
# Add in symbols for the various checks of segment selectors.
for check in ("NoCheck", "CSCheck", "CallGateCheck", "IntGateCheck",
@@ -93,11 +93,11 @@
"TRCheck", "TSSCheck", "InGDTCheck", "LDTCheck"):
assembler.symbols[check] = "Seg%s" % check
- for reg in ("TR", "IDTR"):
- assembler.symbols[reg.lower()] = segRegIdx("SYS_SEGMENT_REG_%s" %
reg)
+ for reg in ("tr", "idtr"):
+ assembler.symbols[reg] =
segRegIdx(f"segment_idx::{reg.capitalize()}")
- for reg in ("TSL", "TSG"):
- assembler.symbols[reg.lower()] = segRegIdx("SEGMENT_REG_%s" % reg)
+ for reg in ("tsl", "tsg"):
+ assembler.symbols[reg] =
segRegIdx(f"segment_idx::{reg.capitalize()}")
# Miscellaneous symbols
symbols = {
@@ -144,10 +144,10 @@
# This segment selects an internal address space mapped to MSRs,
# CPUID info, etc.
- assembler.symbols["intseg"] = segRegIdx("SEGMENT_REG_MS")
+ assembler.symbols["intseg"] = segRegIdx("segment_idx::Ms")
# This segment always has base 0, and doesn't imply any special
handling
# like the internal segment above
- assembler.symbols["flatseg"] = segRegIdx("SEGMENT_REG_LS")
+ assembler.symbols["flatseg"] = segRegIdx("segment_idx::Ls")
for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di', \
'8', '9', '10', '11', '12', '13', '14', '15'):
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index dd7b4a3..78c7f5b 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -127,7 +127,7 @@
class SquashCSReg(SquashCheckReg):
def __init__(self, idx, id, ctype='uqw'):
super(SquashCSReg, self).__init__(
- idx, id, 'dest == X86ISA::SEGMENT_REG_CS', ctype)
+ idx, id, 'dest == X86ISA::segment_idx::Cs', ctype)
class SquashCR0Reg(SquashCheckReg):
def __init__(self, idx, id, ctype='uqw'):
diff --git a/src/arch/x86/isa/specialize.isa
b/src/arch/x86/isa/specialize.isa
index 1ebe0ff..f1ea6d5 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -261,7 +261,7 @@
env.addressSize, false);''')
else:
env.addToDisassembly(
- '''printMem(out, SEGMENT_REG_ES,
+ '''printMem(out, segment_idx::Es,
1, X86ISA::int_reg::NumRegs,
X86ISA::int_reg::Rdi, 0,
env.addressSize, false);''')
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 391db0a..190aa33 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -336,12 +336,12 @@
tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
//Start using longmode segments.
- installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
- installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
- installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
- installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
- installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
- installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
+ installSegDesc(tc, segment_idx::Cs, csDesc, true);
+ installSegDesc(tc, segment_idx::Ds, dsDesc, true);
+ installSegDesc(tc, segment_idx::Es, dsDesc, true);
+ installSegDesc(tc, segment_idx::Fs, dsDesc, true);
+ installSegDesc(tc, segment_idx::Gs, dsDesc, true);
+ installSegDesc(tc, segment_idx::Ss, dsDesc, true);
Efer efer = 0;
efer.sce = 1; // Enable system call extensions.
@@ -540,7 +540,7 @@
dataAttr.system = 1;
// Initialize the segment registers.
- for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
+ for (int seg = 0; seg < segment_idx::NumIdxs; seg++) {
tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
@@ -651,7 +651,7 @@
dataAttr.system = 1;
// Initialize the segment registers.
- for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
+ for (int seg = 0; seg < segment_idx::NumIdxs; seg++) {
tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index 89997dc..89807e9 100644
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -314,7 +314,7 @@
MISCREG_IDTR,
// Hidden segment base field
- MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
+ MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE +
segment_idx::NumIdxs,
MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
MISCREG_CS_BASE,
MISCREG_SS_BASE,
@@ -332,7 +332,8 @@
// The effective segment base, ie what is actually added to an
// address. In 64 bit mode this can be different from the above,
// namely 0.
- MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE +
NUM_SEGMENTREGS,
+ MISCREG_SEG_EFF_BASE_BASE =
+ MISCREG_SEG_BASE_BASE + segment_idx::NumIdxs,
MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
MISCREG_CS_EFF_BASE,
MISCREG_SS_EFF_BASE,
@@ -348,7 +349,8 @@
MISCREG_IDTR_EFF_BASE,
// Hidden segment limit field
- MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE +
NUM_SEGMENTREGS,
+ MISCREG_SEG_LIMIT_BASE =
+ MISCREG_SEG_EFF_BASE_BASE + segment_idx::NumIdxs,
MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
MISCREG_CS_LIMIT,
MISCREG_SS_LIMIT,
@@ -364,7 +366,7 @@
MISCREG_IDTR_LIMIT,
// Hidden segment limit attributes
- MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
+ MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE +
segment_idx::NumIdxs,
MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
MISCREG_CS_ATTR,
MISCREG_SS_ATTR,
@@ -380,8 +382,7 @@
MISCREG_IDTR_ATTR,
// Floating point control registers
- MISCREG_X87_TOP =
- MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
+ MISCREG_X87_TOP = MISCREG_SEG_ATTR_BASE + segment_idx::NumIdxs,
MISCREG_MXCSR,
MISCREG_FCW,
@@ -510,35 +511,35 @@
static inline MiscRegIndex
MISCREG_SEG_SEL(int index)
{
- assert(index >= 0 && index < NUM_SEGMENTREGS);
+ assert(index >= 0 && index < segment_idx::NumIdxs);
return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
}
static inline MiscRegIndex
MISCREG_SEG_BASE(int index)
{
- assert(index >= 0 && index < NUM_SEGMENTREGS);
+ assert(index >= 0 && index < segment_idx::NumIdxs);
return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
}
static inline MiscRegIndex
MISCREG_SEG_EFF_BASE(int index)
{
- assert(index >= 0 && index < NUM_SEGMENTREGS);
+ assert(index >= 0 && index < segment_idx::NumIdxs);
return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
}
static inline MiscRegIndex
MISCREG_SEG_LIMIT(int index)
{
- assert(index >= 0 && index < NUM_SEGMENTREGS);
+ assert(index >= 0 && index < segment_idx::NumIdxs);
return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
}
static inline MiscRegIndex
MISCREG_SEG_ATTR(int index)
{
- assert(index >= 0 && index < NUM_SEGMENTREGS);
+ assert(index >= 0 && index < segment_idx::NumIdxs);
return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
}
diff --git a/src/arch/x86/regs/segment.hh b/src/arch/x86/regs/segment.hh
index 714bc2e..96be72c 100644
--- a/src/arch/x86/regs/segment.hh
+++ b/src/arch/x86/regs/segment.hh
@@ -40,30 +40,34 @@
namespace gem5
{
-
namespace X86ISA
{
- enum SegmentRegIndex
- {
- SEGMENT_REG_ES,
- SEGMENT_REG_CS,
- SEGMENT_REG_SS,
- SEGMENT_REG_DS,
- SEGMENT_REG_FS,
- SEGMENT_REG_GS,
- SEGMENT_REG_HS, // Temporary descriptor
- SEGMENT_REG_TSL, // Local descriptor table
- SEGMENT_REG_TSG, // Global descriptor table
- SEGMENT_REG_LS, // Flat segment
- SEGMENT_REG_MS, // Emulation memory
- // These shouldn't be used directly in a load or store since they
- // are likely accessed in other ways in a real machine. For
instance,
- // they may be loaded into the temporary segment register on
demand.
- SYS_SEGMENT_REG_TR,
- SYS_SEGMENT_REG_IDTR,
+namespace segment_idx
+{
- NUM_SEGMENTREGS
- };
+enum
+{
+ Es,
+ Cs,
+ Ss,
+ Ds,
+ Fs,
+ Gs,
+ Hs, // Temporary descriptor
+ Tsl, // Local descriptor table
+ Tsg, // Global descriptor table
+ Ls, // Flat segment
+ Ms, // Emulation memory
+ // These shouldn't be used directly in a load or store since they
+ // are likely accessed in other ways in a real machine. For instance,
+ // they may be loaded into the temporary segment register on demand.
+ Tr,
+ Idtr,
+
+ NumIdxs
+};
+
+} // namespace segment_idx
} // namespace X86ISA
} // namespace gem5
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 00e1120..d5eabde 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -319,7 +319,7 @@
// If this is true, we're dealing with a request to a non-memory
address
// space.
- if (seg == SEGMENT_REG_MS) {
+ if (seg == segment_idx::Ms) {
return translateInt(mode == BaseMMU::Read, req, tc);
}
@@ -335,13 +335,13 @@
if (m5Reg.mode != LongMode) {
DPRINTF(TLB, "Not in long mode. Checking segment
protection.\n");
// Check for a NULL segment selector.
- if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
- seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
+ if (!(seg == segment_idx::Tsg || seg == segment_idx::Idtr ||
+ seg == segment_idx::Hs || seg == segment_idx::Ls)
&& !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
return std::make_shared<GeneralProtection>(0);
bool expandDown = false;
SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
- if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
+ if (seg >= segment_idx::Es && seg <= segment_idx::Hs) {
if (!attr.writable && (mode == BaseMMU::Write ||
storeCheck))
return std::make_shared<GeneralProtection>(0);
if (!attr.readable && mode == BaseMMU::Read)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I69778c8d052ad6cc0ffd9e74dd1c643e9d28048d
Gerrit-Change-Number: 49756
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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