Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49762 )
Change subject: arch-arm: For semihosting, mask reg value and not index.
......................................................................
arch-arm: For semihosting, mask reg value and not index.
In ArmSemihosting::call64, the *index* of X0 was masked to be 32 bits (a
noop), and then read using the TC, where I'm pretty sure what was
intended was to read the value and then mask what was returned.
Change-Id: I66cb845d4e97b1895072bd98de709256625c8e3f
---
M src/arch/arm/semihosting.cc
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index fc98d6e..ed6fa29 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -169,7 +169,7 @@
bool
ArmSemihosting::call64(ThreadContext *tc, bool gem5_ops)
{
- RegVal op = tc->readIntReg(ArmISA::INTREG_X0 & mask(32));
+ RegVal op = tc->readIntReg(ArmISA::INTREG_X0) & mask(32);
if (op > MaxStandardOp && !gem5_ops) {
unrecognizedCall<Abi64>(
tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I66cb845d4e97b1895072bd98de709256625c8e3f
Gerrit-Change-Number: 49762
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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