Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49766 )
Change subject: arch-arm: Switch from (set|read)Vec* to (get|set)Reg*
accessors.
......................................................................
arch-arm: Switch from (set|read)Vec* to (get|set)Reg* accessors.
Change-Id: I9e9b51b965402b3c8c94cce1593d62aa2118cd0c
---
M src/arch/arm/aapcs32.hh
M src/arch/arm/aapcs64.hh
M src/arch/arm/htm.cc
M src/arch/arm/isa.cc
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/arm/nativetrace.cc
M src/arch/arm/remote_gdb.cc
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_record_v8.cc
M src/arch/arm/utility.cc
10 files changed, 62 insertions(+), 41 deletions(-)
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index f74b787..236df87 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -476,9 +476,10 @@
}
RegId id(VecRegClass, 0);
- auto reg = tc->readVecReg(id);
+ ArmISA::VecRegContainer reg;
+ tc->getReg(id, ®);
reg.as<Float>()[0] = f;
- tc->setVecReg(id, reg);
+ tc->setReg(id, ®);
};
};
@@ -500,7 +501,8 @@
const int lane = index % lane_per_reg;
RegId id(VecRegClass, reg);
- auto val = tc->readVecReg(id);
+ ArmISA::VecRegContainer val;
+ tc->getReg(id, &val);
return val.as<Float>()[lane];
}
@@ -571,7 +573,8 @@
const int lane = index % lane_per_reg;
RegId id(VecRegClass, reg);
- auto val = tc->readVecReg(id);
+ ArmISA::VecRegContainer val;
+ tc->getReg(id, &val);
ha[i] = val.as<Elem>()[lane];
}
return ha;
@@ -618,9 +621,10 @@
const int lane = i % lane_per_reg;
RegId id(VecRegClass, reg);
- auto val = tc->readVecReg(id);
+ ArmISA::VecRegContainer val;
+ tc->getReg(id, &val);
val.as<Elem>()[lane] = ha[i];
- tc->setVecReg(id, val);
+ tc->setReg(id, &val);
}
}
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index 38cd93b..47c2ec4 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -202,7 +202,9 @@
{
if (state.nsrn <= state.MAX_SRN) {
RegId id(VecRegClass, state.nsrn++);
- return tc->readVecReg(id).as<Float>()[0];
+ ArmISA::VecRegContainer vc;
+ tc->getReg(id, &vc);
+ return vc.as<Float>()[0];
}
return loadFromStack<Float>(tc, state);
@@ -217,9 +219,10 @@
store(ThreadContext *tc, const Float &f)
{
RegId id(VecRegClass, 0);
- auto reg = tc->readVecReg(id);
+ ArmISA::VecRegContainer reg;
+ tc->getReg(id, ®);
reg.as<Float>()[0] = f;
- tc->setVecReg(id, reg);
+ tc->setReg(id, ®);
}
};
diff --git a/src/arch/arm/htm.cc b/src/arch/arm/htm.cc
index 50cdad0..9a75cc8 100644
--- a/src/arch/arm/htm.cc
+++ b/src/arch/arm/htm.cc
@@ -82,7 +82,7 @@
// TODO first detect if FP is enabled at this EL
for (auto n = 0; n < NumVecRegs; n++) {
RegId idx = RegId(VecRegClass, n);
- z[n] = tc->readVecReg(idx);
+ tc->getReg(idx, &z[n]);
}
for (auto n = 0; n < NumVecPredRegs; n++) {
RegId idx = RegId(VecPredRegClass, n);
@@ -109,7 +109,7 @@
// TODO first detect if FP is enabled at this EL
for (auto n = 0; n < NumVecRegs; n++) {
RegId idx = RegId(VecRegClass, n);
- tc->setVecReg(idx, z[n]);
+ tc->setReg(idx, &z[n]);
}
for (auto n = 0; n < NumVecPredRegs; n++) {
RegId idx = RegId(VecPredRegClass, n);
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d7424b9..ec45404 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -527,11 +527,17 @@
for (int i = 0; i < NUM_MISCREGS; i++)
tc->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
- for (int i = 0; i < NumVecRegs; i++)
- tc->setVecRegFlat(i, src->readVecRegFlat(i));
+ ArmISA::VecRegContainer vc;
+ for (int i = 0; i < NumVecRegs; i++) {
+ RegId reg(VecRegClass, i);
+ src->getRegFlat(reg, &vc);
+ tc->setRegFlat(reg, &vc);
+ }
- for (int i = 0; i < NumVecRegs * NumVecElemPerVecReg; i++)
- tc->setVecElemFlat(i, src->readVecElemFlat(i));
+ for (int i = 0; i < NumVecRegs * NumVecElemPerVecReg; i++) {
+ RegId reg(VecElemClass, i);
+ tc->setRegFlat(reg, src->getRegFlat(reg));
+ }
// setMiscReg "with effect" will set the misc register mapping
correctly.
// e.g. updateRegMap(val)
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index a1536b9..1b55a1a 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -256,7 +256,9 @@
for (int i = 0; i < NUM_QREGS; ++i) {
KvmFPReg reg;
- auto v = tc->readVecReg(RegId(VecRegClass, i)).as<VecElem>();
+ ArmISA::VecRegContainer vc;
+ tc->getReg(RegId(VecRegClass, i), &vc);
+ auto v = vc.as<VecElem>();
for (int j = 0; j < FP_REGS_PER_VFP_REG; j++)
reg.s[j].i = v[j];
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index dcfb121..24eda53 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -128,7 +128,9 @@
changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
for (int i = 0; i < NumVecV7ArchRegs; i++) {
- auto *vec = tc->readVecReg(RegId(VecRegClass,i)).as<uint64_t>();
+ ArmISA::VecRegContainer vec_container;
+ tc->getReg(RegId(VecRegClass, i), &vec_container);
+ auto *vec = vec_container.as<uint64_t>();
newState[STATE_F0 + 2*i] = vec[0];
newState[STATE_F0 + 2*i + 1] = vec[1];
}
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index cd51aea..e93defc 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -228,7 +228,9 @@
size_t base = 0;
for (int i = 0; i < NumVecV8ArchRegs; i++) {
- auto v = (context->readVecReg(RegId(VecRegClass,
i))).as<VecElem>();
+ ArmISA::VecRegContainer vc;
+ context->getReg(RegId(VecRegClass, i), &vc);
+ auto v = vc.as<VecElem>();
for (size_t j = 0; j < NumVecElemPerNeonVecReg; j++) {
r.v[base] = v[j];
base++;
@@ -256,8 +258,9 @@
size_t base = 0;
for (int i = 0; i < NumVecV8ArchRegs; i++) {
- auto v = (context->getWritableVecReg(
- RegId(VecRegClass, i))).as<VecElem>();
+ auto *vc = static_cast<ArmISA::VecRegContainer *>(
+ context->getWritableReg(RegId(VecRegClass, i)));
+ auto v = vc->as<VecElem>();
for (size_t j = 0; j < NumVecElemPerNeonVecReg; j++) {
v[j] = r.v[base];
base++;
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index bdae48d..ce12625 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -759,26 +759,26 @@
break;
case REG_S:
if (instRecord.isetstate == ISET_A64) {
- const ArmISA::VecRegContainer& vc = thread->readVecReg(
- RegId(VecRegClass, it->index));
+ ArmISA::VecRegContainer vc;
+ thread->getReg(RegId(VecRegClass, it->index), &vc);
auto vv = vc.as<uint32_t>();
values.push_back(vv[0]);
} else {
- const VecElem elem = thread->readVecElem(
+ const VecElem elem = thread->getReg(
RegId(VecElemClass, it->index));
values.push_back(elem);
}
break;
case REG_D:
if (instRecord.isetstate == ISET_A64) {
- const ArmISA::VecRegContainer& vc = thread->readVecReg(
- RegId(VecRegClass, it->index));
+ ArmISA::VecRegContainer vc;
+ thread->getReg(RegId(VecRegClass, it->index), &vc);
auto vv = vc.as<uint64_t>();
values.push_back(vv[0]);
} else {
- const VecElem w0 = thread->readVecElem(
+ const VecElem w0 = thread->getReg(
RegId(VecElemClass, it->index));
- const VecElem w1 = thread->readVecElem(
+ const VecElem w1 = thread->getReg(
RegId(VecElemClass, it->index + 1));
values.push_back((uint64_t)(w1) << 32 | w0);
@@ -798,19 +798,19 @@
break;
case REG_Q:
if (instRecord.isetstate == ISET_A64) {
- const ArmISA::VecRegContainer& vc = thread->readVecReg(
- RegId(VecRegClass, it->index));
+ ArmISA::VecRegContainer vc;
+ thread->getReg(RegId(VecRegClass, it->index), &vc);
auto vv = vc.as<uint64_t>();
values.push_back(vv[0]);
values.push_back(vv[1]);
} else {
- const VecElem w0 = thread->readVecElem(
+ const VecElem w0 = thread->getReg(
RegId(VecElemClass, it->index));
- const VecElem w1 = thread->readVecElem(
+ const VecElem w1 = thread->getReg(
RegId(VecElemClass, it->index + 1));
- const VecElem w2 = thread->readVecElem(
+ const VecElem w2 = thread->getReg(
RegId(VecElemClass, it->index + 2));
- const VecElem w3 = thread->readVecElem(
+ const VecElem w3 = thread->getReg(
RegId(VecElemClass, it->index + 3));
values.push_back((uint64_t)(w1) << 32 | w0);
@@ -820,8 +820,8 @@
case REG_Z:
{
int8_t i = maxVectorLength;
- const ArmISA::VecRegContainer& vc = thread->readVecReg(
- RegId(VecRegClass, it->index));
+ ArmISA::VecRegContainer vc;
+ thread->getReg(RegId(VecRegClass, it->index), &vc);
auto vv = vc.as<uint64_t>();
while (i > 0) {
values.push_back(vv[--i]);
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc
b/src/arch/arm/tracers/tarmac_record_v8.cc
index 30e9d1e..3c4a152 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -138,8 +138,8 @@
)
{
auto thread = tarmCtx.thread;
- const auto& vec_container = thread->readVecReg(
- RegId(regClass, regRelIdx));
+ ArmISA::VecRegContainer vec_container;
+ thread->getReg(RegId(regClass, regRelIdx), &vec_container);
auto vv = vec_container.as<VecElem>();
regWidth = ArmStaticInst::getCurSveVecLenInBits(thread);
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 28692fc..b45297e 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1334,10 +1334,11 @@
int ei = 0;
for (int ri = 0; ri < NumVecRegs; ri++) {
RegId reg_id(VecRegClass, ri);
- const VecRegContainer ® = tc->readVecReg(reg_id);
+ VecRegContainer reg;
+ tc->getReg(reg_id, ®);
for (int j = 0; j < NumVecElemPerVecReg; j++, ei++) {
RegId elem_id(VecElemClass, ei);
- tc->setVecElem(elem_id, reg.as<VecElem>()[j]);
+ tc->setReg(elem_id, reg.as<VecElem>()[j]);
}
}
}
@@ -1350,10 +1351,10 @@
VecRegContainer reg;
for (int j = 0; j < NumVecElemPerVecReg; j++, ei++) {
RegId elem_id(VecElemClass, ei);
- reg.as<VecElem>()[j] = tc->readVecElem(elem_id);
+ reg.as<VecElem>()[j] = tc->getReg(elem_id);
}
RegId reg_id(VecRegClass, ri);
- tc->setVecReg(reg_id, reg);
+ tc->setReg(reg_id, ®);
}
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49766
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9e9b51b965402b3c8c94cce1593d62aa2118cd0c
Gerrit-Change-Number: 49766
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
