Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49779 )
Change subject: arch,cpu: Keep track of the RegClassType of a RegClass.
......................................................................
arch,cpu: Keep track of the RegClassType of a RegClass.
This makes it possible to do more things with a RegClass locally.
Change-Id: Ib7d7fa3e2d88a34d5b5681fcc4aab26696c71205
---
M src/arch/arm/isa.cc
M src/arch/mips/isa.cc
M src/arch/power/isa.cc
M src/arch/riscv/isa.cc
M src/arch/sparc/isa.cc
M src/arch/x86/isa.cc
M src/cpu/reg_class.hh
7 files changed, 76 insertions(+), 52 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ec45404..47f9c1f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -88,16 +88,19 @@
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
{
- _regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
- _regClasses.emplace_back(0, debug::FloatRegs);
- _regClasses.emplace_back(NumVecRegs, vecRegClassOps, debug::VecRegs,
- sizeof(VecRegContainer));
- _regClasses.emplace_back(NumVecRegs * ArmISA::NumVecElemPerVecReg,
- vecRegElemClassOps, debug::VecRegs);
- _regClasses.emplace_back(NumVecPredRegs, vecPredRegClassOps,
- debug::VecPredRegs, sizeof(VecPredRegContainer));
- _regClasses.emplace_back(cc_reg::NumRegs, debug::CCRegs);
- _regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps,
debug::MiscRegs);
+ _regClasses.emplace_back(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
+ _regClasses.emplace_back(FloatRegClass, 0, debug::FloatRegs);
+ _regClasses.emplace_back(VecRegClass, NumVecRegs, vecRegClassOps,
+ debug::VecRegs, sizeof(VecRegContainer));
+ _regClasses.emplace_back(VecElemClass,
+ NumVecRegs * ArmISA::NumVecElemPerVecReg, vecRegElemClassOps,
+ debug::VecRegs);
+ _regClasses.emplace_back(VecPredRegClass, NumVecPredRegs,
+ vecPredRegClassOps, debug::VecPredRegs,
+ sizeof(VecPredRegContainer));
+ _regClasses.emplace_back(CCRegClass, cc_reg::NumRegs, debug::CCRegs);
+ _regClasses.emplace_back(MiscRegClass, NUM_MISCREGS, miscRegClassOps,
+ debug::MiscRegs);
miscRegs[MISCREG_SCTLR_RST] = 0;
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index c1fdf27..81b65b2 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -100,13 +100,17 @@
ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
numVpes(p.num_vpes)
{
- _regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
- _regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
- _regClasses.emplace_back(1, debug::IntRegs); // Not applicable to MIPS.
- _regClasses.emplace_back(2, debug::IntRegs); // Not applicable to MIPS.
- _regClasses.emplace_back(1, debug::IntRegs); // Not applicable to MIPS.
- _regClasses.emplace_back(0, debug::IntRegs); // Not applicable to MIPS.
- _regClasses.emplace_back(misc_reg::NumRegs, debug::MiscRegs);
+ _regClasses.emplace_back(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
+ _regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
+ debug::FloatRegs);
+
+ /* Not applicable to MIPS. */
+ _regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
+ _regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
+ _regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
+ _regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
+
+ _regClasses.emplace_back(MiscRegClass, misc_reg::NumRegs,
debug::MiscRegs);
miscRegFile.resize(misc_reg::NumRegs);
bankType.resize(misc_reg::NumRegs);
diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
index ff9f9b6..38d0d17 100644
--- a/src/arch/power/isa.cc
+++ b/src/arch/power/isa.cc
@@ -54,13 +54,14 @@
ISA::ISA(const Params &p) : BaseISA(p)
{
- _regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
- _regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
- _regClasses.emplace_back(1, debug::IntRegs);
- _regClasses.emplace_back(2, debug::IntRegs);
- _regClasses.emplace_back(1, debug::IntRegs);
- _regClasses.emplace_back(0, debug::IntRegs);
- _regClasses.emplace_back(NUM_MISCREGS, debug::MiscRegs);
+ _regClasses.emplace_back(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
+ _regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
+ debug::FloatRegs);
+ _regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
+ _regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
+ _regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
+ _regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
+ _regClasses.emplace_back(MiscRegClass, NUM_MISCREGS, debug::MiscRegs);
clear();
}
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index bcecdc1..1e47916 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -187,13 +187,17 @@
ISA::ISA(const Params &p) : BaseISA(p)
{
- _regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
- _regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
- _regClasses.emplace_back(1, debug::IntRegs); // Not applicable to RISCV
- _regClasses.emplace_back(2, debug::IntRegs); // Not applicable to RISCV
- _regClasses.emplace_back(1, debug::IntRegs); // Not applicable to RISCV
- _regClasses.emplace_back(0, debug::IntRegs); // Not applicable to RISCV
- _regClasses.emplace_back(NUM_MISCREGS, debug::MiscRegs);
+ _regClasses.emplace_back(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
+ _regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
+ debug::FloatRegs);
+
+ /* Not applicable to RISCV */
+ _regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
+ _regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
+ _regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
+ _regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
+
+ _regClasses.emplace_back(MiscRegClass, NUM_MISCREGS, debug::MiscRegs);
miscRegFile.resize(NUM_MISCREGS);
clear();
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 3d867a4..c3fde76 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -70,13 +70,17 @@
ISA::ISA(const Params &p) : BaseISA(p)
{
- _regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
- _regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
- _regClasses.emplace_back(1, debug::IntRegs); // Not applicable for
SPARC
- _regClasses.emplace_back(2, debug::IntRegs); // Not applicable for
SPARC
- _regClasses.emplace_back(1, debug::IntRegs); // Not applicable for
SPARC
- _regClasses.emplace_back(0, debug::IntRegs); // Not applicable for
SPARC
- _regClasses.emplace_back(NumMiscRegs, debug::MiscRegs);
+ _regClasses.emplace_back(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
+ _regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
+ debug::FloatRegs);
+
+ /* Not applicable for SPARC */
+ _regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
+ _regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
+ _regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
+ _regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
+
+ _regClasses.emplace_back(MiscRegClass, NumMiscRegs, debug::MiscRegs);
clear();
}
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 6704cdc..57dcd53 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -146,13 +146,17 @@
fatal_if(vendorString.size() != 12,
"CPUID vendor string must be 12 characters\n");
- _regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
- _regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
- _regClasses.emplace_back(1, debug::IntRegs); // Not applicable to X86
- _regClasses.emplace_back(2, debug::IntRegs); // Not applicable to X86
- _regClasses.emplace_back(1, debug::IntRegs); // Not applicable to X86
- _regClasses.emplace_back(cc_reg::NumRegs, debug::CCRegs);
- _regClasses.emplace_back(misc_reg::NumRegs, debug::MiscRegs);
+ _regClasses.emplace_back(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
+ _regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
+ debug::FloatRegs);
+
+ /* Not applicable to X86 */
+ _regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
+ _regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
+ _regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
+
+ _regClasses.emplace_back(CCRegClass, cc_reg::NumRegs, debug::CCRegs);
+ _regClasses.emplace_back(MiscRegClass, misc_reg::NumRegs,
debug::MiscRegs);
clear();
}
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 8eb325d..732b10f 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -81,6 +81,8 @@
class RegClass
{
private:
+ RegClassType _type;
+
size_t _size;
size_t _regBytes;
// This is how much to shift an index by to get an offset of a
register in
@@ -93,18 +95,20 @@
const debug::Flag &debugFlag;
public:
- constexpr RegClass(size_t new_size, const debug::Flag &debug_flag,
- size_t reg_bytes=sizeof(RegVal)) :
- _size(new_size), _regBytes(reg_bytes),
_regShift(ceilLog2(reg_bytes)),
- debugFlag(debug_flag)
- {}
- constexpr RegClass(size_t new_size, RegClassOps &new_ops,
+ constexpr RegClass(RegClassType type, size_t new_size,
const debug::Flag &debug_flag, size_t
reg_bytes=sizeof(RegVal)) :
- RegClass(new_size, debug_flag, reg_bytes)
+ _type(type), _size(new_size), _regBytes(reg_bytes),
+ _regShift(ceilLog2(reg_bytes)), debugFlag(debug_flag)
+ {}
+ constexpr RegClass(RegClassType type, size_t new_size,
+ RegClassOps &new_ops, const debug::Flag &debug_flag,
+ size_t reg_bytes=sizeof(RegVal)) :
+ RegClass(type, new_size, debug_flag, reg_bytes)
{
_ops = &new_ops;
}
+ constexpr RegClassType type() const { return _type; }
constexpr size_t size() const { return _size; }
constexpr size_t regBytes() const { return _regBytes; }
constexpr size_t regShift() const { return _regShift; }
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49779
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib7d7fa3e2d88a34d5b5681fcc4aab26696c71205
Gerrit-Change-Number: 49779
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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