[gem5-dev] Change in gem5/gem5[develop]: cpu-minor: Use the << operator in minorTraceInst.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49809 )

Change subject: cpu-minor: Use the << operator in minorTraceInst.
......................................................................

cpu-minor: Use the << operator in minorTraceInst.

Use that to print the RegIds of an inst directly, without having to pass
around the register class vector.

Change-Id: I6e5b06518f4826a1e4e8589c5ed095609d3d02b0
---
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/dyn_inst.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/fetch2.cc
4 files changed, 10 insertions(+), 19 deletions(-)



diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc
index 6dd5133..b6ce1e3 100644
--- a/src/cpu/minor/dyn_inst.cc
+++ b/src/cpu/minor/dyn_inst.cc
@@ -139,10 +139,8 @@
 /** Print a register in the form r<n>, f<n>, m<n>(<name>) for integer,
  *  float, and misc given an 'architectural register number' */
 static void
-printRegName(std::ostream &os, const RegId& reg,
-        const BaseISA::RegClasses &reg_classes)
+printRegName(std::ostream &os, const RegId& reg)
 {
-    const auto &reg_class = *reg_classes.at(reg.classValue());
     switch (reg.classValue()) {
       case InvalidRegClass:
         os << 'z';
@@ -150,7 +148,7 @@
       case MiscRegClass:
         {
             RegIndex misc_reg = reg.index();
-            os << 'm' << misc_reg << '(' << reg_class.regName(reg) << ')';
+            os << 'm' << misc_reg << '(' << reg << ')';
         }
         break;
       case FloatRegClass:
@@ -160,7 +158,7 @@
         os << 'v' << reg.index();
         break;
       case VecElemClass:
-        os << reg_class.regName(reg);
+        os << reg;
         break;
       case IntRegClass:
         os << 'r' << reg.index();
@@ -174,8 +172,7 @@
 }

 void
-MinorDynInst::minorTraceInst(const Named &named_object,
-        const BaseISA::RegClasses &reg_classes) const
+MinorDynInst::minorTraceInst(const Named &named_object) const
 {
     if (isFault()) {
         minorInst(named_object, "id=F;%s addr=0x%x fault=\"%s\"\n",
@@ -193,8 +190,7 @@

             unsigned int src_reg = 0;
             while (src_reg < num_src_regs) {
-                printRegName(regs_str, staticInst->srcRegIdx(src_reg),
-                        reg_classes);
+                printRegName(regs_str, staticInst->srcRegIdx(src_reg));

                 src_reg++;
                 if (src_reg != num_src_regs)
@@ -205,8 +201,7 @@

             unsigned int dest_reg = 0;
             while (dest_reg < num_dest_regs) {
-                printRegName(regs_str, staticInst->destRegIdx(dest_reg),
-                        reg_classes);
+                printRegName(regs_str, staticInst->destRegIdx(dest_reg));

                 dest_reg++;
                 if (dest_reg != num_dest_regs)
diff --git a/src/cpu/minor/dyn_inst.hh b/src/cpu/minor/dyn_inst.hh
index d71ccec..61b89c7 100644
--- a/src/cpu/minor/dyn_inst.hh
+++ b/src/cpu/minor/dyn_inst.hh
@@ -278,8 +278,7 @@

     /** Print (possibly verbose) instruction information for
      *  MinorTrace using the given Named object's name */
-    void minorTraceInst(const Named &named_object,
-            const BaseISA::RegClasses &reg_classes) const;
+    void minorTraceInst(const Named &named_object) const;

     /** ReportIF interface */
     void reportData(std::ostream &os) const;
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 0172c2b..21f0278 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -781,8 +781,7 @@
             /* Generate MinorTrace's MinorInst lines.  Do this at commit
              *  to allow better instruction annotation? */
             if (debug::MinorTrace && !inst->isBubble()) {
-                inst->minorTraceInst(*this,
-                        cpu.threads[0]->getIsaPtr()->regClasses());
+                inst->minorTraceInst(*this);
             }

             /* Mark up barriers in the LSQ */
diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc
index 68c1371..c628576 100644
--- a/src/cpu/minor/fetch2.cc
+++ b/src/cpu/minor/fetch2.cc
@@ -489,10 +489,8 @@
                 /* Output MinorTrace instruction info for
                  *  pre-microop decomposition macroops */
                 if (debug::MinorTrace && !dyn_inst->isFault() &&
-                    dyn_inst->staticInst->isMacroop())
-                {
-                    dyn_inst->minorTraceInst(*this,
-                            cpu.threads[0]->getIsaPtr()->regClasses());
+                    dyn_inst->staticInst->isMacroop()) {
+                    dyn_inst->minorTraceInst(*this);
                 }
             }


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6e5b06518f4826a1e4e8589c5ed095609d3d02b0
Gerrit-Change-Number: 49809
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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