Quentin Forcioli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49988 )
Change subject: arch-arm,dev-arm: Changed IRQ/FIQ behavior
......................................................................
arch-arm,dev-arm: Changed IRQ/FIQ behavior
Taking into account that FIQ and IRQ can
transform into each other when they belong to group 1.
This commit is part of series of commit to enable booting OPTEE on gem5.
Change-Id: I068ecc8b757149aa05d3d500e05e1297a543118f
---
M src/arch/arm/interrupts.cc
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.hh
M src/dev/arm/gic_v3_cpu_interface.hh
4 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/interrupts.cc b/src/arch/arm/interrupts.cc
index b0f18df..7010e6b 100644
--- a/src/arch/arm/interrupts.cc
+++ b/src/arch/arm/interrupts.cc
@@ -36,8 +36,9 @@
*/
#include "arch/arm/interrupts.hh"
-
+#include "arch/arm/isa.hh"
#include "arch/arm/system.hh"
+#include "dev/arm/gic_v3_cpu_interface.hh"
namespace gem5
{
@@ -159,4 +160,16 @@
(mask != INT_MASK_P);
}
+void ArmISA::Interrupts::checkForFiqIrqMutation() const
+{
+ //TODO check if pending IRQ is from G1S or G1NS
+ ISA* isa=static_cast<ISA*>(tc->getIsaPtr());
+ if (isa->haveGICv3CpuIfc()) {
+ Gicv3CPUInterface& interf=dynamic_cast<Gicv3CPUInterface&>(
+ isa->getGICv3CPUInterface()
+ );
+ interf.update();
+ }
+}
+
} // namespace gem5
diff --git a/src/arch/arm/interrupts.hh b/src/arch/arm/interrupts.hh
index 2f99d6e..2bd3dc6 100644
--- a/src/arch/arm/interrupts.hh
+++ b/src/arch/arm/interrupts.hh
@@ -128,6 +128,10 @@
};
bool takeInt(InterruptTypes int_type) const;
+ //this function check for FIQ or IRQ that changed nature of interrupt
+ //because of EL change
+ //(G1NS et G1S IRQ are FIQ if not in the right security setting)
+ void checkForFiqIrqMutation() const;
bool
checkInterrupts() const override
@@ -164,9 +168,15 @@
bool take_irq = takeInt(INT_IRQ);
bool take_fiq = takeInt(INT_FIQ);
bool take_ea = takeInt(INT_ABT);
-
- return ((interrupts[INT_IRQ] && take_irq) ||
- (interrupts[INT_FIQ] && take_fiq) ||
+ bool is_irq =(interrupts[INT_IRQ] && take_irq);
+ bool is_fiq =(interrupts[INT_FIQ] && take_fiq);
+ if (is_irq || is_fiq) {
+ checkForFiqIrqMutation();
+ is_irq =(interrupts[INT_IRQ] && take_irq);
+ is_fiq =(interrupts[INT_FIQ] && take_fiq);
+ }
+ return ( is_irq ||
+ is_fiq ||
(interrupts[INT_ABT] && take_ea) ||
((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq) ||
((interrupts[INT_VIRT_FIQ] || hcr.vf) && allowVFiq) ||
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 0e38483..05755fc 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -499,7 +499,6 @@
}
BaseISADevice &getGenericTimer();
- BaseISADevice &getGICv3CPUInterface();
private:
void assert32() { assert(((CPSR)readMiscReg(MISCREG_CPSR)).width);
}
@@ -889,6 +888,8 @@
return gicv3CpuInterface != nullptr;
}
+ BaseISADevice &getGICv3CPUInterface();
+
enums::VecRegRenameMode
initVecRegRenameMode() const override
{
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh
b/src/dev/arm/gic_v3_cpu_interface.hh
index 9f60d84..fa2ca55 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -53,7 +53,7 @@
class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
{
private:
-
+ friend class ArmISA::Interrupts;
friend class Gicv3Distributor;
friend class Gicv3Redistributor;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49988
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I068ecc8b757149aa05d3d500e05e1297a543118f
Gerrit-Change-Number: 49988
Gerrit-PatchSet: 1
Gerrit-Owner: Quentin Forcioli <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
