Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50336 )
Change subject: scons: Use tags to gate ISA files and not env['TARGET_ISA'].
......................................................................
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
Change-Id: Ib81a4c570fbb050fa7d82919edacfed004c6800e
---
M src/arch/arm/SConscript
M src/arch/arm/fastmodel/CortexA76/SConscript
M src/arch/arm/fastmodel/CortexR52/SConscript
M src/arch/arm/fastmodel/GIC/SConscript
M src/arch/arm/fastmodel/PL330_DMAC/SConscript
M src/arch/arm/gdb-xml/SConscript
M src/arch/arm/kvm/SConscript
M src/arch/arm/tracers/SConscript
M src/arch/mips/SConscript
M src/arch/mips/gdb-xml/SConscript
M src/arch/power/SConscript
M src/arch/power/gdb-xml/SConscript
M src/arch/riscv/SConscript
M src/arch/riscv/gdb-xml/SConscript
M src/arch/riscv/insts/SConscript
M src/arch/sparc/SConscript
M src/arch/sparc/insts/SConscript
M src/arch/x86/SConscript
M src/arch/x86/bios/SConscript
M src/arch/x86/linux/SConscript
M src/arch/x86/regs/SConscript
M src/cpu/kvm/SConscript
M src/dev/amdgpu/SConscript
M src/dev/arm/SConscript
M src/dev/arm/css/SConscript
M src/dev/mips/SConscript
M src/dev/riscv/SConscript
M src/dev/sparc/SConscript
M src/dev/x86/SConscript
29 files changed, 396 insertions(+), 433 deletions(-)
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 024b3fa..3a36624 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -40,78 +40,73 @@
Import('*')
-if env['TARGET_ISA'] == 'arm':
-# Workaround for bug in SCons version > 0.97d20071212
-# Scons bug id: 2006 M5 Bug id: 308
- Dir('isa/formats')
+GTest('aapcs64.test', 'aapcs64.test.cc')
+Source('decoder.cc', tags='arm isa')
+Source('faults.cc', tags='arm isa')
+Source('htm.cc', tags='arm isa')
+Source('insts/branch.cc', tags='arm isa')
+Source('insts/branch64.cc', tags='arm isa')
+Source('insts/data64.cc', tags='arm isa')
+Source('insts/macromem.cc', tags='arm isa')
+Source('insts/mem.cc', tags='arm isa')
+Source('insts/mem64.cc', tags='arm isa')
+Source('insts/misc.cc', tags='arm isa')
+Source('insts/misc64.cc', tags='arm isa')
+Source('insts/pred_inst.cc', tags='arm isa')
+Source('insts/pseudo.cc', tags='arm isa')
+Source('insts/static_inst.cc', tags='arm isa')
+Source('insts/sve.cc', tags='arm isa')
+Source('insts/sve_mem.cc', tags='arm isa')
+Source('insts/vfp.cc', tags='arm isa')
+Source('insts/fplib.cc', tags='arm isa')
+Source('insts/crypto.cc', tags='arm isa')
+Source('insts/tme64.cc', tags='arm isa')
+if env['PROTOCOL'] == 'MESI_Three_Level_HTM':
+ Source('insts/tme64ruby.cc', tags='arm isa')
+else:
+ Source('insts/tme64classic.cc', tags='arm isa')
+Source('interrupts.cc', tags='arm isa')
+Source('isa.cc', tags='arm isa')
+Source('isa_device.cc', tags='arm isa')
+Source('linux/process.cc', tags='arm isa')
+Source('linux/se_workload.cc', tags='arm isa')
+Source('linux/fs_workload.cc', tags='arm isa')
+Source('freebsd/fs_workload.cc', tags='arm isa')
+Source('freebsd/se_workload.cc', tags='arm isa')
+Source('fs_workload.cc', tags='arm isa')
+Source('regs/misc.cc', tags='arm isa')
+Source('mmu.cc', tags='arm isa')
+Source('nativetrace.cc', tags='arm isa')
+Source('pauth_helpers.cc', tags='arm isa')
+Source('pmu.cc', tags='arm isa')
+Source('process.cc', tags='arm isa')
+Source('qarma.cc', tags='arm isa')
+Source('remote_gdb.cc', tags='arm isa')
+Source('reg_abi.cc', tags='arm isa')
+Source('semihosting.cc', tags='arm isa')
+Source('system.cc', tags='arm isa')
+Source('table_walker.cc', tags='arm isa')
+Source('self_debug.cc', tags='arm isa')
+Source('stage2_lookup.cc', tags='arm isa')
+Source('tlb.cc', tags='arm isa')
+Source('tlbi_op.cc', tags='arm isa')
+Source('utility.cc', tags='arm isa')
- GTest('aapcs64.test', 'aapcs64.test.cc')
- Source('decoder.cc')
- Source('faults.cc')
- Source('htm.cc')
- Source('insts/branch.cc')
- Source('insts/branch64.cc')
- Source('insts/data64.cc')
- Source('insts/macromem.cc')
- Source('insts/mem.cc')
- Source('insts/mem64.cc')
- Source('insts/misc.cc')
- Source('insts/misc64.cc')
- Source('insts/pred_inst.cc')
- Source('insts/pseudo.cc')
- Source('insts/static_inst.cc')
- Source('insts/sve.cc')
- Source('insts/sve_mem.cc')
- Source('insts/vfp.cc')
- Source('insts/fplib.cc')
- Source('insts/crypto.cc')
- Source('insts/tme64.cc')
- if env['PROTOCOL'] == 'MESI_Three_Level_HTM':
- Source('insts/tme64ruby.cc')
- else:
- Source('insts/tme64classic.cc')
- Source('interrupts.cc')
- Source('isa.cc')
- Source('isa_device.cc')
- Source('linux/process.cc')
- Source('linux/se_workload.cc')
- Source('linux/fs_workload.cc')
- Source('freebsd/fs_workload.cc')
- Source('freebsd/se_workload.cc')
- Source('fs_workload.cc')
- Source('regs/misc.cc')
- Source('mmu.cc')
- Source('nativetrace.cc')
- Source('pauth_helpers.cc')
- Source('pmu.cc')
- Source('process.cc')
- Source('qarma.cc')
- Source('remote_gdb.cc')
- Source('reg_abi.cc')
- Source('semihosting.cc')
- Source('system.cc')
- Source('table_walker.cc')
- Source('self_debug.cc')
- Source('stage2_lookup.cc')
- Source('tlb.cc')
- Source('tlbi_op.cc')
- Source('utility.cc')
+SimObject('ArmFsWorkload.py', tags='arm isa')
+SimObject('ArmInterrupts.py', tags='arm isa')
+SimObject('ArmISA.py', tags='arm isa')
+SimObject('ArmMMU.py', tags='arm isa')
+SimObject('ArmNativeTrace.py', tags='arm isa')
+SimObject('ArmSemihosting.py', tags='arm isa')
+SimObject('ArmSeWorkload.py', tags='arm isa')
+SimObject('ArmSystem.py', tags='arm isa')
+SimObject('ArmTLB.py', tags='arm isa')
+SimObject('ArmPMU.py', tags='arm isa')
- SimObject('ArmFsWorkload.py')
- SimObject('ArmInterrupts.py')
- SimObject('ArmISA.py')
- SimObject('ArmMMU.py')
- SimObject('ArmNativeTrace.py')
- SimObject('ArmSemihosting.py')
- SimObject('ArmSeWorkload.py')
- SimObject('ArmSystem.py')
- SimObject('ArmTLB.py')
- SimObject('ArmPMU.py')
+DebugFlag('Arm', tags='arm isa')
+DebugFlag('ArmTme', 'Transactional Memory Extension', tags='arm isa')
+DebugFlag('Semihosting', tags='arm isa')
+DebugFlag('PMUVerbose', "Performance Monitor", tags='arm isa')
- DebugFlag('Arm')
- DebugFlag('ArmTme', 'Transactional Memory Extension')
- DebugFlag('Semihosting')
- DebugFlag('PMUVerbose', "Performance Monitor")
-
- # Add files generated by the ISA description.
- ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6)
+# Add files generated by the ISA description.
+ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6, tags='arm isa')
diff --git a/src/arch/arm/fastmodel/CortexA76/SConscript
b/src/arch/arm/fastmodel/CortexA76/SConscript
index 883e0ae..376d068 100644
--- a/src/arch/arm/fastmodel/CortexA76/SConscript
+++ b/src/arch/arm/fastmodel/CortexA76/SConscript
@@ -25,7 +25,7 @@
Import('*')
-if not env['USE_ARM_FASTMODEL'] or env['TARGET_ISA'] != 'arm':
+if not env['USE_ARM_FASTMODEL']:
Return()
protocol_dir = Dir('..').Dir('protocol')
diff --git a/src/arch/arm/fastmodel/CortexR52/SConscript
b/src/arch/arm/fastmodel/CortexR52/SConscript
index 3f7a2c8..0b81fbb 100644
--- a/src/arch/arm/fastmodel/CortexR52/SConscript
+++ b/src/arch/arm/fastmodel/CortexR52/SConscript
@@ -25,7 +25,7 @@
Import('*')
-if not env['USE_ARM_FASTMODEL'] or env['TARGET_ISA'] != 'arm':
+if not env['USE_ARM_FASTMODEL']:
Return()
protocol_dir = Dir('..').Dir('protocol')
diff --git a/src/arch/arm/fastmodel/GIC/SConscript
b/src/arch/arm/fastmodel/GIC/SConscript
index 94d2050..94cfbb9 100644
--- a/src/arch/arm/fastmodel/GIC/SConscript
+++ b/src/arch/arm/fastmodel/GIC/SConscript
@@ -25,7 +25,7 @@
Import('*')
-if not env['USE_ARM_FASTMODEL'] or env['TARGET_ISA'] != 'arm':
+if not env['USE_ARM_FASTMODEL']:
Return()
protocol_dir = Dir('..').Dir('protocol')
diff --git a/src/arch/arm/fastmodel/PL330_DMAC/SConscript
b/src/arch/arm/fastmodel/PL330_DMAC/SConscript
index 97f15f6..4640b93 100644
--- a/src/arch/arm/fastmodel/PL330_DMAC/SConscript
+++ b/src/arch/arm/fastmodel/PL330_DMAC/SConscript
@@ -25,7 +25,7 @@
Import('*')
-if not env['USE_ARM_FASTMODEL'] or env['TARGET_ISA'] != 'arm':
+if not env['USE_ARM_FASTMODEL']:
Return()
protocol_dir = Dir('..').Dir('protocol')
diff --git a/src/arch/arm/gdb-xml/SConscript
b/src/arch/arm/gdb-xml/SConscript
index 83097ef..b80749c 100644
--- a/src/arch/arm/gdb-xml/SConscript
+++ b/src/arch/arm/gdb-xml/SConscript
@@ -40,10 +40,9 @@
Import('*')
-if env['TARGET_ISA'] == 'arm':
- GdbXml('arm-with-neon.xml', 'gdb_xml_arm_target')
- GdbXml('arm-core.xml', 'gdb_xml_arm_core')
- GdbXml('arm-vfpv3.xml', 'gdb_xml_arm_vfpv3')
- GdbXml('aarch64.xml', 'gdb_xml_aarch64_target')
- GdbXml('aarch64-core.xml', 'gdb_xml_aarch64_core')
- GdbXml('aarch64-fpu.xml', 'gdb_xml_aarch64_fpu')
+GdbXml('arm-with-neon.xml', 'gdb_xml_arm_target', tags='arm isa')
+GdbXml('arm-core.xml', 'gdb_xml_arm_core', tags='arm isa')
+GdbXml('arm-vfpv3.xml', 'gdb_xml_arm_vfpv3', tags='arm isa')
+GdbXml('aarch64.xml', 'gdb_xml_aarch64_target', tags='arm isa')
+GdbXml('aarch64-core.xml', 'gdb_xml_aarch64_core', tags='arm isa')
+GdbXml('aarch64-fpu.xml', 'gdb_xml_aarch64_fpu', tags='arm isa')
diff --git a/src/arch/arm/kvm/SConscript b/src/arch/arm/kvm/SConscript
index b078f06..3adb45c 100644
--- a/src/arch/arm/kvm/SConscript
+++ b/src/arch/arm/kvm/SConscript
@@ -40,19 +40,18 @@
import platform
host_isa = platform.machine()
-if not (env['USE_KVM'] and env['TARGET_ISA'] == 'arm' and
- env['KVM_ISA'] == 'arm'):
+if not (env['USE_KVM'] and env['KVM_ISA'] == 'arm'):
Return()
-SimObject('KvmGic.py')
-Source('gic.cc')
+SimObject('KvmGic.py', tags='arm isa')
+Source('gic.cc', tags='arm isa')
-SimObject('BaseArmKvmCPU.py')
-Source('base_cpu.cc')
+SimObject('BaseArmKvmCPU.py', tags='arm isa')
+Source('base_cpu.cc', tags='arm isa')
if host_isa == "armv7l":
- SimObject('ArmKvmCPU.py')
- Source('arm_cpu.cc')
+ SimObject('ArmKvmCPU.py', tags='arm isa')
+ Source('arm_cpu.cc', tags='arm isa')
elif host_isa == "aarch64":
- SimObject('ArmV8KvmCPU.py')
- Source('armv8_cpu.cc')
+ SimObject('ArmV8KvmCPU.py', tags='arm isa')
+ Source('armv8_cpu.cc', tags='arm isa')
diff --git a/src/arch/arm/tracers/SConscript
b/src/arch/arm/tracers/SConscript
index 6c03a0d..3ea03aa 100644
--- a/src/arch/arm/tracers/SConscript
+++ b/src/arch/arm/tracers/SConscript
@@ -35,10 +35,9 @@
Import('*')
-if env['TARGET_ISA'] == 'arm':
- SimObject('TarmacTrace.py')
- Source('tarmac_base.cc')
- Source('tarmac_parser.cc')
- Source('tarmac_tracer.cc')
- Source('tarmac_record.cc')
- Source('tarmac_record_v8.cc')
+SimObject('TarmacTrace.py', tags='arm isa')
+Source('tarmac_base.cc', tags='arm isa')
+Source('tarmac_parser.cc', tags='arm isa')
+Source('tarmac_tracer.cc', tags='arm isa')
+Source('tarmac_record.cc', tags='arm isa')
+Source('tarmac_record_v8.cc', tags='arm isa')
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 839bc37..26be9f6 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -29,27 +29,26 @@
Import('*')
-if env['TARGET_ISA'] == 'mips':
- Source('decoder.cc')
- Source('dsp.cc')
- Source('faults.cc')
- Source('idle_event.cc')
- Source('interrupts.cc')
- Source('isa.cc')
- Source('linux/se_workload.cc')
- Source('pagetable.cc')
- Source('process.cc')
- Source('remote_gdb.cc')
- Source('se_workload.cc')
- Source('tlb.cc')
- Source('utility.cc')
+Source('decoder.cc', tags='mips isa')
+Source('dsp.cc', tags='mips isa')
+Source('faults.cc', tags='mips isa')
+Source('idle_event.cc', tags='mips isa')
+Source('interrupts.cc', tags='mips isa')
+Source('isa.cc', tags='mips isa')
+Source('linux/se_workload.cc', tags='mips isa')
+Source('pagetable.cc', tags='mips isa')
+Source('process.cc', tags='mips isa')
+Source('remote_gdb.cc', tags='mips isa')
+Source('se_workload.cc', tags='mips isa')
+Source('tlb.cc', tags='mips isa')
+Source('utility.cc', tags='mips isa')
- SimObject('MipsInterrupts.py')
- SimObject('MipsISA.py')
- SimObject('MipsMMU.py')
- SimObject('MipsSeWorkload.py')
- SimObject('MipsTLB.py')
+SimObject('MipsInterrupts.py', tags='mips isa')
+SimObject('MipsISA.py', tags='mips isa')
+SimObject('MipsMMU.py', tags='mips isa')
+SimObject('MipsSeWorkload.py', tags='mips isa')
+SimObject('MipsTLB.py', tags='mips isa')
- DebugFlag('MipsPRA')
+DebugFlag('MipsPRA', tags='mips isa')
- ISADesc('isa/main.isa')
+ISADesc('isa/main.isa', tags='mips isa')
diff --git a/src/arch/mips/gdb-xml/SConscript
b/src/arch/mips/gdb-xml/SConscript
index a2a1afa..b1d8d6f 100644
--- a/src/arch/mips/gdb-xml/SConscript
+++ b/src/arch/mips/gdb-xml/SConscript
@@ -29,5 +29,4 @@
Import('*')
-if env['TARGET_ISA'] == 'mips':
- GdbXml('mips.xml', 'gdb_xml_mips')
+GdbXml('mips.xml', 'gdb_xml_mips', tags='mips isa')
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index 7138cdb..b26525b 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -30,32 +30,28 @@
Import('*')
-if env['TARGET_ISA'] == 'power':
-# Workaround for bug in SCons version > 0.97d20071212
-# Scons bug id: 2006 M5 Bug id: 308
- Dir('isa/formats')
- Source('decoder.cc')
- Source('faults.cc')
- Source('insts/branch.cc')
- Source('insts/mem.cc')
- Source('insts/integer.cc')
- Source('insts/floating.cc')
- Source('insts/condition.cc')
- Source('insts/static_inst.cc')
- Source('linux/se_workload.cc')
- Source('isa.cc')
- Source('pagetable.cc')
- Source('process.cc')
- Source('remote_gdb.cc')
- Source('se_workload.cc')
- Source('tlb.cc')
+Source('decoder.cc', tags='power isa')
+Source('faults.cc', tags='power isa')
+Source('insts/branch.cc', tags='power isa')
+Source('insts/mem.cc', tags='power isa')
+Source('insts/integer.cc', tags='power isa')
+Source('insts/floating.cc', tags='power isa')
+Source('insts/condition.cc', tags='power isa')
+Source('insts/static_inst.cc', tags='power isa')
+Source('linux/se_workload.cc', tags='power isa')
+Source('isa.cc', tags='power isa')
+Source('pagetable.cc', tags='power isa')
+Source('process.cc', tags='power isa')
+Source('remote_gdb.cc', tags='power isa')
+Source('se_workload.cc', tags='power isa')
+Source('tlb.cc', tags='power isa')
- SimObject('PowerInterrupts.py')
- SimObject('PowerISA.py')
- SimObject('PowerMMU.py')
- SimObject('PowerSeWorkload.py')
- SimObject('PowerTLB.py')
+SimObject('PowerInterrupts.py', tags='power isa')
+SimObject('PowerISA.py', tags='power isa')
+SimObject('PowerMMU.py', tags='power isa')
+SimObject('PowerSeWorkload.py', tags='power isa')
+SimObject('PowerTLB.py', tags='power isa')
- DebugFlag('Power')
+DebugFlag('Power', tags='power isa')
- ISADesc('isa/main.isa')
+ISADesc('isa/main.isa', tags='power isa')
diff --git a/src/arch/power/gdb-xml/SConscript
b/src/arch/power/gdb-xml/SConscript
index 58b874e..6610a3a 100644
--- a/src/arch/power/gdb-xml/SConscript
+++ b/src/arch/power/gdb-xml/SConscript
@@ -30,9 +30,8 @@
Import('*')
-if env['TARGET_ISA'] == 'power':
- GdbXml('power-core.xml', 'gdb_xml_power_core')
- GdbXml('power64-core.xml', 'gdb_xml_power64_core')
- GdbXml('power-fpu.xml', 'gdb_xml_power_fpu')
- GdbXml('powerpc-32.xml', 'gdb_xml_powerpc_32')
- GdbXml('powerpc-64.xml', 'gdb_xml_powerpc_64')
+GdbXml('power-core.xml', 'gdb_xml_power_core', tags='power isa')
+GdbXml('power64-core.xml', 'gdb_xml_power64_core', tags='power isa')
+GdbXml('power-fpu.xml', 'gdb_xml_power_fpu', tags='power isa')
+GdbXml('powerpc-32.xml', 'gdb_xml_powerpc_32', tags='power isa')
+GdbXml('powerpc-64.xml', 'gdb_xml_powerpc_64', tags='power isa')
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index b6ae654..3027440 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -43,36 +43,35 @@
Import('*')
-if env['TARGET_ISA'] == 'riscv':
- Source('decoder.cc')
- Source('faults.cc')
- Source('isa.cc')
- Source('locked_mem.cc')
- Source('process.cc')
- Source('pagetable.cc')
- Source('pagetable_walker.cc')
- Source('pma_checker.cc')
- Source('pmp.cc')
- Source('reg_abi.cc')
- Source('remote_gdb.cc')
- Source('tlb.cc')
+Source('decoder.cc', tags='riscv isa')
+Source('faults.cc', tags='riscv isa')
+Source('isa.cc', tags='riscv isa')
+Source('locked_mem.cc', tags='riscv isa')
+Source('process.cc', tags='riscv isa')
+Source('pagetable.cc', tags='riscv isa')
+Source('pagetable_walker.cc', tags='riscv isa')
+Source('pma_checker.cc', tags='riscv isa')
+Source('pmp.cc', tags='riscv isa')
+Source('reg_abi.cc', tags='riscv isa')
+Source('remote_gdb.cc', tags='riscv isa')
+Source('tlb.cc', tags='riscv isa')
- Source('linux/se_workload.cc')
- Source('linux/fs_workload.cc')
+Source('linux/se_workload.cc', tags='riscv isa')
+Source('linux/fs_workload.cc', tags='riscv isa')
- Source('bare_metal/fs_workload.cc')
+Source('bare_metal/fs_workload.cc', tags='riscv isa')
- SimObject('PMAChecker.py')
- SimObject('PMP.py')
- SimObject('RiscvFsWorkload.py')
- SimObject('RiscvInterrupts.py')
- SimObject('RiscvISA.py')
- SimObject('RiscvMMU.py')
- SimObject('RiscvSeWorkload.py')
- SimObject('RiscvTLB.py')
+SimObject('PMAChecker.py', tags='riscv isa')
+SimObject('PMP.py', tags='riscv isa')
+SimObject('RiscvFsWorkload.py', tags='riscv isa')
+SimObject('RiscvInterrupts.py', tags='riscv isa')
+SimObject('RiscvISA.py', tags='riscv isa')
+SimObject('RiscvMMU.py', tags='riscv isa')
+SimObject('RiscvSeWorkload.py', tags='riscv isa')
+SimObject('RiscvTLB.py', tags='riscv isa')
- DebugFlag('RiscvMisc')
- DebugFlag('PMP')
+DebugFlag('RiscvMisc', tags='riscv isa')
+DebugFlag('PMP', tags='riscv isa')
- # Add in files generated by the ISA description.
- ISADesc('isa/main.isa')
+# Add in files generated by the ISA description.
+ISADesc('isa/main.isa', tags='riscv isa')
diff --git a/src/arch/riscv/gdb-xml/SConscript
b/src/arch/riscv/gdb-xml/SConscript
index e4fdf91..a733b1e 100644
--- a/src/arch/riscv/gdb-xml/SConscript
+++ b/src/arch/riscv/gdb-xml/SConscript
@@ -43,8 +43,7 @@
Import('*')
-if env['TARGET_ISA'] == 'riscv':
- GdbXml('riscv.xml', 'gdb_xml_riscv_target')
- GdbXml('riscv-64bit-cpu.xml', 'gdb_xml_riscv_cpu')
- GdbXml('riscv-64bit-fpu.xml', 'gdb_xml_riscv_fpu')
- GdbXml('riscv-64bit-csr.xml', 'gdb_xml_riscv_csr')
+GdbXml('riscv.xml', 'gdb_xml_riscv_target', tags='riscv isa')
+GdbXml('riscv-64bit-cpu.xml', 'gdb_xml_riscv_cpu', tags='riscv isa')
+GdbXml('riscv-64bit-fpu.xml', 'gdb_xml_riscv_fpu', tags='riscv isa')
+GdbXml('riscv-64bit-csr.xml', 'gdb_xml_riscv_csr', tags='riscv isa')
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index d9e47c3..80592a3 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -27,9 +27,8 @@
Import('*')
-if env['TARGET_ISA'] == 'riscv':
- Source('amo.cc')
- Source('compressed.cc')
- Source('mem.cc')
- Source('standard.cc')
- Source('static_inst.cc')
+Source('amo.cc', tags='riscv isa')
+Source('compressed.cc', tags='riscv isa')
+Source('mem.cc', tags='riscv isa')
+Source('standard.cc', tags='riscv isa')
+Source('static_inst.cc', tags='riscv isa')
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index d17caa9..2a15847 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -28,31 +28,30 @@
Import('*')
-if env['TARGET_ISA'] == 'sparc':
- Source('asi.cc')
- Source('decoder.cc')
- Source('faults.cc')
- Source('fs_workload.cc')
- Source('isa.cc')
- Source('linux/se_workload.cc')
- Source('linux/syscalls.cc')
- Source('nativetrace.cc')
- Source('pagetable.cc')
- Source('process.cc')
- Source('remote_gdb.cc')
- Source('se_workload.cc')
- Source('tlb.cc')
- Source('ua2005.cc')
+Source('asi.cc', tags='sparc isa')
+Source('decoder.cc', tags='sparc isa')
+Source('faults.cc', tags='sparc isa')
+Source('fs_workload.cc', tags='sparc isa')
+Source('isa.cc', tags='sparc isa')
+Source('linux/se_workload.cc', tags='sparc isa')
+Source('linux/syscalls.cc', tags='sparc isa')
+Source('nativetrace.cc', tags='sparc isa')
+Source('pagetable.cc', tags='sparc isa')
+Source('process.cc', tags='sparc isa')
+Source('remote_gdb.cc', tags='sparc isa')
+Source('se_workload.cc', tags='sparc isa')
+Source('tlb.cc', tags='sparc isa')
+Source('ua2005.cc', tags='sparc isa')
- SimObject('SparcFsWorkload.py')
- SimObject('SparcInterrupts.py')
- SimObject('SparcISA.py')
- SimObject('SparcMMU.py')
- SimObject('SparcNativeTrace.py')
- SimObject('SparcSeWorkload.py')
- SimObject('SparcTLB.py')
+SimObject('SparcFsWorkload.py', tags='sparc isa')
+SimObject('SparcInterrupts.py', tags='sparc isa')
+SimObject('SparcISA.py', tags='sparc isa')
+SimObject('SparcMMU.py', tags='sparc isa')
+SimObject('SparcNativeTrace.py', tags='sparc isa')
+SimObject('SparcSeWorkload.py', tags='sparc isa')
+SimObject('SparcTLB.py', tags='sparc isa')
- DebugFlag('Sparc', "Generic SPARC ISA stuff")
- DebugFlag('RegisterWindows', "Register window manipulation")
+DebugFlag('Sparc', "Generic SPARC ISA stuff", tags='sparc isa')
+DebugFlag('RegisterWindows', "Register window manipulation", tags='sparc
isa')
- ISADesc('isa/main.isa')
+ISADesc('isa/main.isa', tags='sparc isa')
diff --git a/src/arch/sparc/insts/SConscript
b/src/arch/sparc/insts/SConscript
index de4e114..ab57bb7 100644
--- a/src/arch/sparc/insts/SConscript
+++ b/src/arch/sparc/insts/SConscript
@@ -28,12 +28,11 @@
Import('*')
-if env['TARGET_ISA'] == 'sparc':
- Source('blockmem.cc')
- Source('branch.cc')
- Source('integer.cc')
- Source('mem.cc')
- Source('micro.cc')
- Source('priv.cc')
- Source('static_inst.cc')
- Source('trap.cc')
+Source('blockmem.cc', tags='sparc isa')
+Source('branch.cc', tags='sparc isa')
+Source('integer.cc', tags='sparc isa')
+Source('mem.cc', tags='sparc isa')
+Source('micro.cc', tags='sparc isa')
+Source('priv.cc', tags='sparc isa')
+Source('static_inst.cc', tags='sparc isa')
+Source('trap.cc', tags='sparc isa')
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 1252116..a455ded 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -40,41 +40,38 @@
Import('*')
-if env['TARGET_ISA'] != 'x86':
- Return()
+Source('cpuid.cc', tags='x86 isa')
+Source('decoder.cc', tags='x86 isa')
+Source('decoder_tables.cc', tags='x86 isa')
+Source('emulenv.cc', tags='x86 isa')
+Source('faults.cc', tags='x86 isa')
+Source('fs_workload.cc', tags='x86 isa')
+Source('insts/badmicroop.cc', tags='x86 isa')
+Source('insts/microop.cc', tags='x86 isa')
+Source('insts/microregop.cc', tags='x86 isa')
+Source('insts/static_inst.cc', tags='x86 isa')
+Source('interrupts.cc', tags='x86 isa')
+Source('isa.cc', tags='x86 isa')
+Source('nativetrace.cc', tags='x86 isa')
+Source('pagetable.cc', tags='x86 isa')
+Source('pagetable_walker.cc', tags='x86 isa')
+Source('process.cc', tags='x86 isa')
+Source('remote_gdb.cc', tags='x86 isa')
+Source('tlb.cc', tags='x86 isa')
+Source('types.cc', tags='x86 isa')
+Source('utility.cc', tags='x86 isa')
-Source('cpuid.cc')
-Source('decoder.cc')
-Source('decoder_tables.cc')
-Source('emulenv.cc')
-Source('faults.cc')
-Source('fs_workload.cc')
-Source('insts/badmicroop.cc')
-Source('insts/microop.cc')
-Source('insts/microregop.cc')
-Source('insts/static_inst.cc')
-Source('interrupts.cc')
-Source('isa.cc')
-Source('nativetrace.cc')
-Source('pagetable.cc')
-Source('pagetable_walker.cc')
-Source('process.cc')
-Source('remote_gdb.cc')
-Source('tlb.cc')
-Source('types.cc')
-Source('utility.cc')
+SimObject('X86SeWorkload.py', tags='x86 isa')
+SimObject('X86FsWorkload.py', tags='x86 isa')
+SimObject('X86ISA.py', tags='x86 isa')
+SimObject('X86LocalApic.py', tags='x86 isa')
+SimObject('X86MMU.py', tags='x86 isa')
+SimObject('X86NativeTrace.py', tags='x86 isa')
+SimObject('X86TLB.py', tags='x86 isa')
-SimObject('X86SeWorkload.py')
-SimObject('X86FsWorkload.py')
-SimObject('X86ISA.py')
-SimObject('X86LocalApic.py')
-SimObject('X86MMU.py')
-SimObject('X86NativeTrace.py')
-SimObject('X86TLB.py')
-
-DebugFlag('LocalApic', "Local APIC debugging")
-DebugFlag('X86', "Generic X86 ISA debugging")
-DebugFlag('ACPI', "ACPI debugging")
+DebugFlag('LocalApic', "Local APIC debugging", tags='x86 isa')
+DebugFlag('X86', "Generic X86 ISA debugging", tags='x86 isa')
+DebugFlag('ACPI', "ACPI debugging", tags='x86 isa')
python_files = (
'__init__.py',
@@ -303,7 +300,7 @@
# Add in files generated by the ISA description.
-isa_desc_files = ISADesc('isa/main.isa')
+isa_desc_files = ISADesc('isa/main.isa', tags='x86 isa')
for f in isa_desc_files:
# Add in python file dependencies that won't be caught otherwise
for pyfile in python_files:
diff --git a/src/arch/x86/bios/SConscript b/src/arch/x86/bios/SConscript
index ce9f5bd..6ecc830 100644
--- a/src/arch/x86/bios/SConscript
+++ b/src/arch/x86/bios/SConscript
@@ -37,20 +37,19 @@
Import('*')
-if env['TARGET_ISA'] == 'x86':
- # The table generated by the bootloader using the BIOS and passed to
- # the operating system which maps out physical memory.
- SimObject('E820.py')
- Source('e820.cc')
+# The table generated by the bootloader using the BIOS and passed to
+# the operating system which maps out physical memory.
+SimObject('E820.py', tags='x86 isa')
+Source('e820.cc', tags='x86 isa')
- # The DMI tables.
- SimObject('SMBios.py')
- Source('smbios.cc')
+# The DMI tables.
+SimObject('SMBios.py', tags='x86 isa')
+Source('smbios.cc', tags='x86 isa')
- # Intel Multiprocessor Specification Configuration Table
- SimObject('IntelMP.py')
- Source('intelmp.cc')
+# Intel Multiprocessor Specification Configuration Table
+SimObject('IntelMP.py', tags='x86 isa')
+Source('intelmp.cc', tags='x86 isa')
- # ACPI system description tables
- SimObject('ACPI.py')
- Source('acpi.cc')
+# ACPI system description tables
+SimObject('ACPI.py', tags='x86 isa')
+Source('acpi.cc', tags='x86 isa')
diff --git a/src/arch/x86/linux/SConscript b/src/arch/x86/linux/SConscript
index d27d6be..429884c 100644
--- a/src/arch/x86/linux/SConscript
+++ b/src/arch/x86/linux/SConscript
@@ -40,11 +40,8 @@
Import('*')
-if env['TARGET_ISA'] != 'x86':
- Return()
-
-Source('fs_workload.cc')
-Source('se_workload.cc')
-Source('syscalls.cc')
-Source('syscall_tbl32.cc')
-Source('syscall_tbl64.cc')
+Source('fs_workload.cc', tags='x86 isa')
+Source('se_workload.cc', tags='x86 isa')
+Source('syscalls.cc', tags='x86 isa')
+Source('syscall_tbl32.cc', tags='x86 isa')
+Source('syscall_tbl64.cc', tags='x86 isa')
diff --git a/src/arch/x86/regs/SConscript b/src/arch/x86/regs/SConscript
index a21e06a..25e0677 100644
--- a/src/arch/x86/regs/SConscript
+++ b/src/arch/x86/regs/SConscript
@@ -28,5 +28,4 @@
Import('*')
-if env['TARGET_ISA'] == 'x86':
- Source('msr.cc')
+Source('msr.cc', tags='x86 isa')
diff --git a/src/cpu/kvm/SConscript b/src/cpu/kvm/SConscript
index 0e79501..3d1e479 100644
--- a/src/cpu/kvm/SConscript
+++ b/src/cpu/kvm/SConscript
@@ -49,9 +49,8 @@
Source('perfevent.cc')
Source('timer.cc')
-if env['TARGET_ISA'] == 'x86':
- SimObject('X86KvmCPU.py')
- Source('x86_cpu.cc')
+SimObject('X86KvmCPU.py', tags='x86 isa')
+Source('x86_cpu.cc', tags='x86 isa')
DebugFlag('Kvm', 'Basic KVM Functionality')
DebugFlag('KvmContext', 'KVM/gem5 context synchronization')
diff --git a/src/dev/amdgpu/SConscript b/src/dev/amdgpu/SConscript
index 7c67e4c..eeff32e 100644
--- a/src/dev/amdgpu/SConscript
+++ b/src/dev/amdgpu/SConscript
@@ -31,13 +31,13 @@
Import('*')
-if env['TARGET_ISA'] != 'x86' or not env['BUILD_GPU']:
+if not env['BUILD_GPU']:
Return()
# Controllers
-SimObject('AMDGPU.py')
+SimObject('AMDGPU.py', tags='x86 isa')
-Source('amdgpu_device.cc')
-Source('mmio_reader.cc')
+Source('amdgpu_device.cc', tags='x86 isa')
+Source('mmio_reader.cc', tags='x86 isa')
-DebugFlag('AMDGPUDevice')
+DebugFlag('AMDGPUDevice', tags='x86 isa')
diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript
index a33b37d..cfbacdb 100644
--- a/src/dev/arm/SConscript
+++ b/src/dev/arm/SConscript
@@ -37,78 +37,77 @@
Import('*')
-if env['TARGET_ISA'] == 'arm':
- SimObject('AbstractNVM.py')
- SimObject('Display.py')
- SimObject('Doorbell.py')
- SimObject('FlashDevice.py')
- SimObject('GenericTimer.py')
- SimObject('Gic.py')
- SimObject('RealView.py')
- SimObject('SMMUv3.py')
- SimObject('UFSHostDevice.py')
- SimObject('EnergyCtrl.py')
- SimObject('NoMali.py')
- SimObject('VirtIOMMIO.py')
- if env['USE_ARM_FASTMODEL']:
- SimObject('VExpressFastmodel.py')
+SimObject('AbstractNVM.py', tags='arm isa')
+SimObject('Display.py', tags='arm isa')
+SimObject('Doorbell.py', tags='arm isa')
+SimObject('FlashDevice.py', tags='arm isa')
+SimObject('GenericTimer.py', tags='arm isa')
+SimObject('Gic.py', tags='arm isa')
+SimObject('RealView.py', tags='arm isa')
+SimObject('SMMUv3.py', tags='arm isa')
+SimObject('UFSHostDevice.py', tags='arm isa')
+SimObject('EnergyCtrl.py', tags='arm isa')
+SimObject('NoMali.py', tags='arm isa')
+SimObject('VirtIOMMIO.py', tags='arm isa')
+if env['USE_ARM_FASTMODEL']:
+ SimObject('VExpressFastmodel.py', tags='arm isa')
- Source('a9scu.cc')
- Source('amba_device.cc')
- Source('amba_fake.cc')
- Source('base_gic.cc')
- Source('display.cc')
- Source('flash_device.cc')
- Source('generic_timer.cc')
- Source('gic_v2.cc')
- Source('gic_v2m.cc')
- Source('gic_v3.cc')
- Source('gic_v3_cpu_interface.cc')
- Source('gic_v3_distributor.cc')
- Source('gic_v3_redistributor.cc')
- Source('gic_v3_its.cc')
- Source('pl011.cc')
- Source('pl111.cc')
- Source('hdlcd.cc')
- Source('kmi.cc')
- Source('smmu_v3.cc');
- Source('smmu_v3_caches.cc');
- Source('smmu_v3_cmdexec.cc');
- Source('smmu_v3_events.cc');
- Source('smmu_v3_ports.cc');
- Source('smmu_v3_proc.cc');
- Source('smmu_v3_ptops.cc');
- Source('smmu_v3_deviceifc.cc');
- Source('smmu_v3_transl.cc');
- Source('timer_sp804.cc')
- Source('watchdog_generic.cc')
- Source('watchdog_sp805.cc')
- Source('gpu_nomali.cc')
- Source('pci_host.cc')
- Source('rv_ctrl.cc')
- Source('realview.cc')
- Source('rtc_pl031.cc')
- Source('timer_cpulocal.cc')
- Source('vgic.cc')
- Source('vio_mmio.cc')
- Source('ufs_device.cc')
- Source('energy_ctrl.cc')
- Source('fvp_base_pwr_ctrl.cc')
+Source('a9scu.cc', tags='arm isa')
+Source('amba_device.cc', tags='arm isa')
+Source('amba_fake.cc', tags='arm isa')
+Source('base_gic.cc', tags='arm isa')
+Source('display.cc', tags='arm isa')
+Source('flash_device.cc', tags='arm isa')
+Source('generic_timer.cc', tags='arm isa')
+Source('gic_v2.cc', tags='arm isa')
+Source('gic_v2m.cc', tags='arm isa')
+Source('gic_v3.cc', tags='arm isa')
+Source('gic_v3_cpu_interface.cc', tags='arm isa')
+Source('gic_v3_distributor.cc', tags='arm isa')
+Source('gic_v3_redistributor.cc', tags='arm isa')
+Source('gic_v3_its.cc', tags='arm isa')
+Source('pl011.cc', tags='arm isa')
+Source('pl111.cc', tags='arm isa')
+Source('hdlcd.cc', tags='arm isa')
+Source('kmi.cc', tags='arm isa')
+Source('smmu_v3.cc', tags='arm isa');
+Source('smmu_v3_caches.cc', tags='arm isa');
+Source('smmu_v3_cmdexec.cc', tags='arm isa');
+Source('smmu_v3_events.cc', tags='arm isa');
+Source('smmu_v3_ports.cc', tags='arm isa');
+Source('smmu_v3_proc.cc', tags='arm isa');
+Source('smmu_v3_ptops.cc', tags='arm isa');
+Source('smmu_v3_deviceifc.cc', tags='arm isa');
+Source('smmu_v3_transl.cc', tags='arm isa');
+Source('timer_sp804.cc', tags='arm isa')
+Source('watchdog_generic.cc', tags='arm isa')
+Source('watchdog_sp805.cc', tags='arm isa')
+Source('gpu_nomali.cc', tags='arm isa')
+Source('pci_host.cc', tags='arm isa')
+Source('rv_ctrl.cc', tags='arm isa')
+Source('realview.cc', tags='arm isa')
+Source('rtc_pl031.cc', tags='arm isa')
+Source('timer_cpulocal.cc', tags='arm isa')
+Source('vgic.cc', tags='arm isa')
+Source('vio_mmio.cc', tags='arm isa')
+Source('ufs_device.cc', tags='arm isa')
+Source('energy_ctrl.cc', tags='arm isa')
+Source('fvp_base_pwr_ctrl.cc', tags='arm isa')
- DebugFlag('AMBA')
- DebugFlag('FlashDevice')
- DebugFlag('HDLcd')
- DebugFlag('PL111')
- DebugFlag('GICV2M')
- DebugFlag('Pl050')
- DebugFlag('GIC')
- DebugFlag('ITS')
- DebugFlag('RVCTRL')
- DebugFlag('SMMUv3')
- DebugFlag('SMMUv3Hazard')
- DebugFlag('Sp805')
- DebugFlag('EnergyCtrl')
- DebugFlag('FVPBasePwrCtrl')
- DebugFlag('UFSHostDevice')
- DebugFlag('VGIC')
- DebugFlag('NoMali')
+DebugFlag('AMBA', tags='arm isa')
+DebugFlag('FlashDevice', tags='arm isa')
+DebugFlag('HDLcd', tags='arm isa')
+DebugFlag('PL111', tags='arm isa')
+DebugFlag('GICV2M', tags='arm isa')
+DebugFlag('Pl050', tags='arm isa')
+DebugFlag('GIC', tags='arm isa')
+DebugFlag('ITS', tags='arm isa')
+DebugFlag('RVCTRL', tags='arm isa')
+DebugFlag('SMMUv3', tags='arm isa')
+DebugFlag('SMMUv3Hazard', tags='arm isa')
+DebugFlag('Sp805', tags='arm isa')
+DebugFlag('EnergyCtrl', tags='arm isa')
+DebugFlag('FVPBasePwrCtrl', tags='arm isa')
+DebugFlag('UFSHostDevice', tags='arm isa')
+DebugFlag('VGIC', tags='arm isa')
+DebugFlag('NoMali', tags='arm isa')
diff --git a/src/dev/arm/css/SConscript b/src/dev/arm/css/SConscript
index 763d119..b57a296 100644
--- a/src/dev/arm/css/SConscript
+++ b/src/dev/arm/css/SConscript
@@ -37,14 +37,13 @@
Import('*')
-if env['TARGET_ISA'] == 'arm':
- SimObject('MHU.py')
- SimObject('Scmi.py')
- SimObject('Scp.py')
+SimObject('MHU.py', tags='arm isa')
+SimObject('Scmi.py', tags='arm isa')
+SimObject('Scp.py', tags='arm isa')
- Source('mhu.cc')
- Source('scmi_platform.cc')
- Source('scmi_protocols.cc')
+Source('mhu.cc', tags='arm isa')
+Source('scmi_platform.cc', tags='arm isa')
+Source('scmi_protocols.cc', tags='arm isa')
- DebugFlag('MHU')
- DebugFlag('SCMI')
+DebugFlag('MHU', tags='arm isa')
+DebugFlag('SCMI', tags='arm isa')
diff --git a/src/dev/mips/SConscript b/src/dev/mips/SConscript
index bf79b3e..b1250a2 100755
--- a/src/dev/mips/SConscript
+++ b/src/dev/mips/SConscript
@@ -28,12 +28,10 @@
Import('*')
-if env['TARGET_ISA'] == 'mips':
- SimObject('Malta.py')
+SimObject('Malta.py', tags='mips isa')
- DebugFlag('Malta')
+DebugFlag('Malta', tags='mips isa')
- Source('malta.cc')
- Source('malta_cchip.cc')
- Source('malta_io.cc')
-
+Source('malta.cc', tags='mips isa')
+Source('malta_cchip.cc', tags='mips isa')
+Source('malta_io.cc', tags='mips isa')
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
index 7de03bf..23f1074 100755
--- a/src/dev/riscv/SConscript
+++ b/src/dev/riscv/SConscript
@@ -28,22 +28,20 @@
Import('*')
-if env['TARGET_ISA'] == 'riscv':
+SimObject('HiFive.py', tags='riscv isa')
+SimObject('Clint.py', tags='riscv isa')
+SimObject('PlicDevice.py', tags='riscv isa')
+SimObject('Plic.py', tags='riscv isa')
+SimObject('RTC.py', tags='riscv isa')
+SimObject('RiscvVirtIOMMIO.py', tags='riscv isa')
- SimObject('HiFive.py')
- SimObject('Clint.py')
- SimObject('PlicDevice.py')
- SimObject('Plic.py')
- SimObject('RTC.py')
- SimObject('RiscvVirtIOMMIO.py')
+DebugFlag('Clint', tags='riscv isa')
+DebugFlag('Plic', tags='riscv isa')
+DebugFlag('VirtIOMMIO', tags='riscv isa')
- DebugFlag('Clint')
- DebugFlag('Plic')
- DebugFlag('VirtIOMMIO')
-
- Source('hifive.cc')
- Source('clint.cc')
- Source('plic_device.cc')
- Source('plic.cc')
- Source('rtc.cc')
- Source('vio_mmio.cc')
+Source('hifive.cc', tags='riscv isa')
+Source('clint.cc', tags='riscv isa')
+Source('plic_device.cc', tags='riscv isa')
+Source('plic.cc', tags='riscv isa')
+Source('rtc.cc', tags='riscv isa')
+Source('vio_mmio.cc', tags='riscv isa')
diff --git a/src/dev/sparc/SConscript b/src/dev/sparc/SConscript
index f85e6a8..d61b9ea 100644
--- a/src/dev/sparc/SConscript
+++ b/src/dev/sparc/SConscript
@@ -28,12 +28,11 @@
Import('*')
-if env['TARGET_ISA'] == 'sparc':
- SimObject('T1000.py')
+SimObject('T1000.py', tags='sparc isa')
- Source('dtod.cc')
- Source('iob.cc')
- Source('t1000.cc')
- Source('mm_disk.cc')
+Source('dtod.cc', tags='sparc isa')
+Source('iob.cc', tags='sparc isa')
+Source('t1000.cc', tags='sparc isa')
+Source('mm_disk.cc', tags='sparc isa')
- DebugFlag('Iob')
+DebugFlag('Iob', tags='sparc isa')
diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript
index 6c81c53..6bee57d 100644
--- a/src/dev/x86/SConscript
+++ b/src/dev/x86/SConscript
@@ -28,37 +28,36 @@
Import('*')
-if env['TARGET_ISA'] == 'x86':
- SimObject('Pc.py')
- Source('pc.cc')
+SimObject('Pc.py', tags='x86 isa')
+Source('pc.cc', tags='x86 isa')
- SimObject('SouthBridge.py')
- Source('south_bridge.cc')
+SimObject('SouthBridge.py', tags='x86 isa')
+Source('south_bridge.cc', tags='x86 isa')
- SimObject('Cmos.py')
- Source('cmos.cc')
- DebugFlag('CMOS', 'Accesses to CMOS devices')
+SimObject('Cmos.py', tags='x86 isa')
+Source('cmos.cc', tags='x86 isa')
+DebugFlag('CMOS', 'Accesses to CMOS devices', tags='x86 isa')
- SimObject('I8259.py')
- Source('i8259.cc')
- DebugFlag('I8259', 'Accesses to the I8259 PIC devices')
+SimObject('I8259.py', tags='x86 isa')
+Source('i8259.cc', tags='x86 isa')
+DebugFlag('I8259', 'Accesses to the I8259 PIC devices', tags='x86 isa')
- SimObject('I8254.py')
- Source('i8254.cc')
- DebugFlag('I8254', 'Interrupts from the I8254 timer');
+SimObject('I8254.py', tags='x86 isa')
+Source('i8254.cc', tags='x86 isa')
+DebugFlag('I8254', 'Interrupts from the I8254 timer', tags='x86 isa');
- SimObject('I8237.py')
- Source('i8237.cc')
- DebugFlag('I8237', 'The I8237 dma controller');
+SimObject('I8237.py', tags='x86 isa')
+Source('i8237.cc', tags='x86 isa')
+DebugFlag('I8237', 'The I8237 dma controller', tags='x86 isa');
- SimObject('I8042.py')
- Source('i8042.cc')
- DebugFlag('I8042', 'The I8042 keyboard controller');
+SimObject('I8042.py', tags='x86 isa')
+Source('i8042.cc', tags='x86 isa')
+DebugFlag('I8042', 'The I8042 keyboard controller', tags='x86 isa');
- SimObject('PcSpeaker.py')
- Source('speaker.cc')
- DebugFlag('PcSpeaker')
+SimObject('PcSpeaker.py', tags='x86 isa')
+Source('speaker.cc', tags='x86 isa')
+DebugFlag('PcSpeaker', tags='x86 isa')
- SimObject('I82094AA.py')
- Source('i82094aa.cc')
- DebugFlag('I82094AA')
+SimObject('I82094AA.py', tags='x86 isa')
+Source('i82094aa.cc', tags='x86 isa')
+DebugFlag('I82094AA', tags='x86 isa')
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib81a4c570fbb050fa7d82919edacfed004c6800e
Gerrit-Change-Number: 50336
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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