Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50390 )
Change subject: arch-arm: Implement Armv8.2 FEAT_UAO
......................................................................
arch-arm: Implement Armv8.2 FEAT_UAO
Change-Id: I87b25a65e706ed6486347806a540b1dbf25231cb
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/ArmISA.py
M src/arch/arm/faults.cc
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa.cc
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
M src/arch/arm/regs/misc_types.hh
M src/arch/arm/utility.cc
10 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 55dcdf4..23338d1 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -116,8 +116,8 @@
# PAN | HPDS | !VHE | VMIDBits
id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101020,
"AArch64 Memory Model Feature Register 1")
- # |VARANGE
- id_aa64mmfr2_el1 = Param.UInt64(0x0000000000010000,
+ # |VARANGE | UAO
+ id_aa64mmfr2_el1 = Param.UInt64(0x0000000000010010,
"AArch64 Memory Model Feature Register 2")
# Any access (read/write) to an unimplemented
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 102ce84..9f82e50 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -677,6 +677,7 @@
ITSTATE it = tc->pcState().itstate();
spsr.it2 = it.top6;
spsr.it1 = it.bottom2;
+ spsr.uao = 0;
}
tc->setMiscReg(spsr_idx, spsr);
@@ -701,6 +702,7 @@
cpsr.il = 0;
cpsr.ss = 0;
cpsr.pan = span ? 1 : spsr.pan;
+ cpsr.uao = 0;
tc->setMiscReg(MISCREG_CPSR, cpsr);
// If we have a valid instruction then use it to annotate this fault
with
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 0f301b0..4cdd3dd 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -800,11 +800,14 @@
RegVal
MiscRegImmOp64::miscRegImm() const
{
- if (dest == MISCREG_SPSEL) {
+ switch (dest) {
+ case MISCREG_SPSEL:
return imm & 0x1;
- } else if (dest == MISCREG_PAN) {
+ case MISCREG_PAN:
return (imm & 0x1) << 22;
- } else {
+ case MISCREG_UAO:
+ return (imm & 0x1) << 23;
+ default:
panic("Not a valid PSTATE field register\n");
}
}
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index d6ca535..b89acbc 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1192,6 +1192,7 @@
} else {
// aarch64
new_cpsr.daif = spsr.daif;
+ new_cpsr.uao = spsr.uao;
}
SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 52042e2..f9ac845 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -773,6 +773,10 @@
{
return miscRegs[MISCREG_CPSR] & 0x400000;
}
+ case MISCREG_UAO:
+ {
+ return miscRegs[MISCREG_CPSR] & 0x800000;
+ }
case MISCREG_L2CTLR:
{
// mostly unimplemented, just set NumCPUs field from sim and
return
@@ -2262,6 +2266,17 @@
misc_reg = MISCREG_CPSR;
}
break;
+ case MISCREG_UAO:
+ {
+ // UAO is affecting data accesses
+ getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
+
+ CPSR cpsr = miscRegs[MISCREG_CPSR];
+ cpsr.uao = (uint8_t) ((CPSR) newVal).uao;
+ newVal = cpsr;
+ misc_reg = MISCREG_CPSR;
+ }
+ break;
case MISCREG_AT_S1E1R_Xt:
addressTranslation64(MMU::S1E1Tran, BaseMMU::Read, 0, val);
return;
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index a508b30..0c67645 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -413,6 +413,10 @@
// MSR immediate: moving immediate value to
selected
// bits of the PSTATE
switch (op1 << 3 | op2) {
+ case 0x3:
+ // UAO
+ return new MsrImm64(
+ machInst, MISCREG_UAO, crm);
case 0x4:
// PAN
return new MsrImm64(
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 3d679bb..4a94a3e 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2451,6 +2451,8 @@
return MISCREG_CURRENTEL;
case 3:
return MISCREG_PAN;
+ case 4:
+ return MISCREG_UAO;
}
break;
case 6:
@@ -4945,6 +4947,8 @@
InitReg(MISCREG_PAN)
.allPrivileges().exceptUserMode()
.implemented(havePAN);
+ InitReg(MISCREG_UAO)
+ .allPrivileges().exceptUserMode();
InitReg(MISCREG_NZCV)
.allPrivileges();
InitReg(MISCREG_DAIF)
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 0e9825d..1a2f137 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1091,6 +1091,7 @@
// PSTATE
MISCREG_PAN,
+ MISCREG_UAO,
// Total number of Misc Registers: Physical + Dummy
NUM_MISCREGS
@@ -2181,6 +2182,7 @@
// PSTATE
"pan",
+ "uao",
};
static_assert(sizeof(miscRegName) / sizeof(*miscRegName) ==
NUM_MISCREGS,
diff --git a/src/arch/arm/regs/misc_types.hh
b/src/arch/arm/regs/misc_types.hh
index 3d1a1a6..05b00e2 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -55,6 +55,7 @@
Bitfield<27> q;
Bitfield<26, 25> it1;
Bitfield<24> j;
+ Bitfield<23> uao; // AArch64
Bitfield<22> pan;
Bitfield<21> ss; // AArch64
Bitfield<20> il; // AArch64
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index c4331a4..0caab64 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1245,6 +1245,8 @@
isUnpriviledgeAccess(ThreadContext *tc)
{
const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+ const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+
// NV Extension not implemented yet
bool have_nv_ext = false;
bool unpriv_el1 = currEL(tc) == EL1 &&
@@ -1254,7 +1256,7 @@
currEL(tc) == EL2 && hcr.e2h == 1 && hcr.tge == 1;
// User Access override, or UAO not implemented yet.
- bool user_access_override = false;
+ bool user_access_override = cpsr.uao;
return (unpriv_el1 || unpriv_el2) && !user_access_override;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I87b25a65e706ed6486347806a540b1dbf25231cb
Gerrit-Change-Number: 50390
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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