Austin Harris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50467 )
Change subject: tests: Add a test for forking and switching cpus
......................................................................
tests: Add a test for forking and switching cpus
This tests forking gem5 and simulating the child with a different cpu.
The test boots linux with the KVM cpu, tests instruction scheduling exit
events, and then forks gem5. The child simulation switches to the
specified cpu and simulates to completion while the parents waits for
the child to finish before also simulating to completion.
Change-Id: I68d7515bf125c855eefc62ba4798cd7c745ef2b0
---
A tests/gem5/configs/components-library/boot_kvm_fork_run.py
1 file changed, 300 insertions(+), 0 deletions(-)
diff --git a/tests/gem5/configs/components-library/boot_kvm_fork_run.py
b/tests/gem5/configs/components-library/boot_kvm_fork_run.py
new file mode 100644
index 0000000..eaf3aabe
--- /dev/null
+++ b/tests/gem5/configs/components-library/boot_kvm_fork_run.py
@@ -0,0 +1,300 @@
+# Copyright (c) 2021 The University of Texas at Austin
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Author: Austin Harris
+#
+
+"""
+This script tests forking gem5 with the KVM cores and switching cores in
the
+child process. First, the test boots linux with KVM and tests
fast-forwarding
+with instruction exit events. Then the test forks the simulation, waits
for the
+child to simulate until completion, and then simulates to completion in the
+parent process.
+"""
+
+import argparse
+import os
+import sys
+from textwrap import dedent
+
+import m5
+from m5.objects import Root
+
+# This is a lame hack to get the imports working correctly.
+# TODO: This needs fixed.
+sys.path.append(
+ os.path.join(
+ os.path.dirname(os.path.abspath(__file__)),
+ os.pardir,
+ os.pardir,
+ os.pardir,
+ os.pardir,
+ )
+)
+
+from components_library.boards.x86_board import X86Board
+from components_library.coherence_protocol import CoherenceProtocol
+from components_library.isas import ISA
+from components_library.memory.single_channel import SingleChannelDDR3_1600
+from components_library.processors.cpu_types import CPUTypes
+from components_library.processors.simple_switchable_processor import (
+ SimpleSwitchableProcessor,
+)
+from components_library.resources.resource import Resource
+from components_library.runtime import (
+ get_runtime_coherence_protocol,
+ get_runtime_isa
+)
+from components_library.utils.requires import requires
+
+parser = argparse.ArgumentParser(
+ description="A script to test forking gem5 and switching cpus."
+)
+parser.add_argument(
+ "-m",
+ "--mem-system",
+ type=str,
+ choices=("classic", "mi_example", "mesi_two_level"),
+ required=True,
+ help="The memory system.",
+)
+parser.add_argument(
+ "-n",
+ "--num-cpus",
+ type=int,
+ choices=(1, 2, 4, 8),
+ default=4,
+ help="The number of CPUs.",
+)
+parser.add_argument(
+ "-c",
+ "--cpu",
+ type=str,
+ choices=("kvm", "atomic", "timing", "o3"),
+ required=True,
+ help="The CPU type.",
+)
+parser.add_argument(
+ "-r",
+ "--resource-directory",
+ type=str,
+ required=False,
+ help="The directory in which resources will be downloaded or exist.",
+)
+parser.add_argument(
+ "-o",
+ "--override-download",
+ action="store_true",
+ help="Override a local resource if the hashes do not match.",
+)
+parser.add_argument(
+ "-k",
+ "--kernel-args",
+ type=str,
+ default="init=/root/gem5_init.sh",
+ help="Additional kernel boot arguments.",
+)
+
+args = parser.parse_args()
+
+coherence_protocol_required = None
+if args.mem_system == "mi_example":
+ coherence_protocol_required = CoherenceProtocol.MI_EXAMPLE
+elif args.mem_system == "mesi_two_level":
+ coherence_protocol_required = CoherenceProtocol.MESI_TWO_LEVEL
+
+requires(
+ isa_required=ISA.X86,
+ coherence_protocol_required=coherence_protocol_required,
+ kvm_required=(args.cpu == "kvm"),
+)
+
+cache_hierarchy = None
+if args.mem_system == "mi_example":
+ from components_library.cachehierarchies.ruby.\
+ mi_example_cache_hierarchy import (
+ MIExampleCacheHierarchy,
+ )
+
+ cache_hierarchy = MIExampleCacheHierarchy(size="32kB", assoc=8)
+elif args.mem_system == "mesi_two_level":
+ from components_library.cachehierarchies.ruby.\
+ mesi_two_level_cache_hierarchy import (
+ MESITwoLevelCacheHierarchy,
+ )
+
+ cache_hierarchy = MESITwoLevelCacheHierarchy(
+ l1d_size="16kB",
+ l1d_assoc=8,
+ l1i_size="16kB",
+ l1i_assoc=8,
+ l2_size="256kB",
+ l2_assoc=16,
+ num_l2_banks=1,
+ )
+elif args.mem_system == "classic":
+ from components_library.cachehierarchies.classic.\
+ private_l1_cache_hierarchy import (
+ PrivateL1CacheHierarchy,
+ )
+
+ cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB",
l1i_size="16kB")
+else:
+ raise NotImplementedError(
+ "Memory system '{}' is not supported in the boot tests.".format(
+ args.mem_system
+ )
+ )
+
+assert cache_hierarchy != None
+
+# Setup the system memory.
+
+memory = SingleChannelDDR3_1600(size="3GB")
+
+# Setup a Processor.
+
+cpu_type = None
+if args.cpu == "kvm":
+ cpu_type = CPUTypes.KVM
+elif args.cpu == "atomic":
+ cpu_type = CPUTypes.ATOMIC
+elif args.cpu == "timing":
+ cpu_type = CPUTypes.TIMING
+elif args.cpu == "o3":
+ cpu_type = CPUTypes.O3
+else:
+ raise NotImplementedError(
+ "CPU type '{}' is not supported in the boot
tests.".format(args.cpu)
+ )
+
+assert cpu_type != None
+
+processor = SimpleSwitchableProcessor(
+ starting_core_type=CPUTypes.KVM,
+ switch_core_type=cpu_type,
+ num_cores=args.num_cpus,
+)
+
+# Setup the motherboard.
+motherboard = X86Board(
+ clk_freq="3GHz",
+ processor=processor,
+ memory=memory,
+ cache_hierarchy=cache_hierarchy,
+ exit_on_work_items=True,
+)
+
+motherboard.connect_things()
+
+# Set the Full System workload.
+motherboard.set_workload(
+ kernel=Resource(
+ "x86-linux-kernel-5.4.49",
+ override=args.override_download,
+ resource_directory=args.resource_directory,
+ ),
+ disk_image=Resource(
+ "x86-boot-exit",
+ override=args.override_download,
+ resource_directory=args.resource_directory,
+ ),
+ command=dedent(
+ """
+ m5 exit
+ #Execute some dummy instructions so we don't m5 exit
+ #before the instruction schedule exit event
+ dd if=/dev/zero of=/tmp/tmp bs=1G count=1
+ rm -f /tmp/tmp
+ m5 exit #signal end of instruction test
+ m5 exit #actually exit
+ """
+ ),
+ kernel_args=[args.kernel_args]
+)
+
+
+# Begin running of the simulation. This will exit once the Linux system
boot
+# is complete.
+print("Running with ISA: " + get_runtime_isa().name)
+print("Running with protocol: " + get_runtime_coherence_protocol().name)
+print()
+
+root = Root(full_system=True, system=motherboard)
+
+# TODO: This of annoying. Is there a way to fix this to happen
+# automatically when running KVM?
+root.sim_quantum = int(1e9)
+
+# Disable the gdb ports. Required for forking.
+m5.disableAllListeners()
+
+m5.instantiate()
+
+# Simulate the inital boot with the starting KVM cpu
+exit_event = m5.simulate()
+print("Boot finished", exit_event.getCause())
+
+# Test fast-forwarding KVM core by instructions
+print("Testing fast forward")
+for core in processor.get_cores():
+ exit_inst = core.core.totalInsts() + 10000
+ core.core.scheduleInstStop(0, exit_inst, "Max Insts CPU 0")
+ print(f"Scheduling core {core} exit at {exit_inst}")
+
+exit_event = m5.simulate()
+if not exit_event.getCause().startswith("Max Insts CPU"):
+ raise Exception(
+ f"Failed to fast forward KVM CPUs! Cause: {exit_event.getCause()}"
+ )
+
+# Skip instruction stop events for the cores scheduled before and
+# complete dummy instructions
+exit_event = m5.simulate()
+while exit_event.getCause().startswith("Max Insts CPU"):
+ exit_event = m5.simulate()
+if exit_event.getCause() != "m5_exit instruction encountered":
+ raise Exception("Expected m5 exit instruction after scheduling test.")
+
+print("Finished KVM fast forwarding test.")
+
+print("Starting fork and switch processors test")
+pid = m5.fork("%(parent)s/" + str(m5.curTick()))
+if pid == 0: # in child
+ print("Switching processors in child.")
+ processor.switch()
+ exit_event = m5.simulate()
+ print("Child finished, exiting: ", exit_event.getCause())
+ sys.exit(0)
+
+print("Waiting for child...")
+os.waitpid(pid, 0)
+
+print("Child finished!")
+exit_event = m5.simulate()
+print(
+ "Exiting @ tick {} because {}.".format(m5.curTick(),
exit_event.getCause())
+)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50467
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I68d7515bf125c855eefc62ba4798cd7c745ef2b0
Gerrit-Change-Number: 50467
Gerrit-PatchSet: 1
Gerrit-Owner: Austin Harris <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
