Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50527 )
Change subject: arch-arm: Remove unused TLBType
......................................................................
arch-arm: Remove unused TLBType
The cached state is global now (per-MMU)
Change-Id: I70bc847813086f678b4ff32722b7f6e3ceaae6f5
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50527
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/isa.cc
M src/arch/arm/mmu.cc
M src/arch/arm/mmu.hh
3 files changed, 4 insertions(+), 14 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 8d5addc..9439d0e 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -905,10 +905,7 @@
CPSR old_cpsr = miscRegs[MISCREG_CPSR];
int old_mode = old_cpsr.mode;
CPSR cpsr = val;
- if (cpsr.pan != old_cpsr.pan) {
- getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
- }
- if (cpsr.il != old_cpsr.il) {
+ if (cpsr.pan != old_cpsr.pan || cpsr.il != old_cpsr.il) {
getMMUPtr(tc)->invalidateMiscReg();
}
@@ -2271,7 +2268,7 @@
case MISCREG_PAN:
{
// PAN is affecting data accesses
- getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
+ getMMUPtr(tc)->invalidateMiscReg();
CPSR cpsr = miscRegs[MISCREG_CPSR];
cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc
index d2fc706..5f0b64e 100644
--- a/src/arch/arm/mmu.cc
+++ b/src/arch/arm/mmu.cc
@@ -160,7 +160,7 @@
}
void
-MMU::invalidateMiscReg(TLBType type)
+MMU::invalidateMiscReg()
{
s1State.miscRegValid = false;
}
diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index 0e1fd87..f6ebd89 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -117,13 +117,6 @@
S12E1Tran = 0x100
};
- enum TLBType
- {
- I_TLBS = 0x01,
- D_TLBS = 0x10,
- ALL_TLBS = 0x11
- };
-
struct CachedState {
explicit CachedState(MMU *_mmu, bool stage2)
: mmu(_mmu), isStage2(stage2)
@@ -250,7 +243,7 @@
void takeOverFrom(BaseMMU *old_mmu) override;
- void invalidateMiscReg(TLBType type = ALL_TLBS);
+ void invalidateMiscReg();
template <typename OP>
void
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I70bc847813086f678b4ff32722b7f6e3ceaae6f5
Gerrit-Change-Number: 50527
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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