[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Define ArmFault::invoke32 to match invoke64

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50507 )

Change subject: arch-arm: Define ArmFault::invoke32 to match invoke64
......................................................................
arch-arm: Define ArmFault::invoke32 to match invoke64

Just providing some symmetry to the ArmFault::invoke method

Change-Id: I244e69eee684b9935bea49cf28c6ed99a01192bf
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50507
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 17 insertions(+), 10 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 102ce84..69366af 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -497,15 +497,20 @@
     if (to64) {
         // Invoke exception handler in AArch64 state
         invoke64(tc, inst);
-        return;
+    } else {
+        // Invoke exception handler in AArch32 state
+        invoke32(tc, inst);
     }
+}

+void
+ArmFault::invoke32(ThreadContext *tc, const StaticInstPtr &inst)
+{
     if (vectorCatch(tc, inst))
         return;

     // ARMv7 (ARM ARM issue C B1.9)
-
-    bool have_security       = ArmSystem::haveSecurity(tc);
+    bool have_security = ArmSystem::haveSecurity(tc);

     FaultBase::invoke(tc);
     if (!FullSystem)
@@ -520,7 +525,7 @@
     saved_cpsr.v = tc->readCCReg(CCREG_V);
     saved_cpsr.ge = tc->readCCReg(CCREG_GE);

-    [[maybe_unused]] Addr curPc = tc->pcState().pc();
+    [[maybe_unused]] Addr cur_pc = tc->pcState().pc();
     ITSTATE it = tc->pcState().itstate();
     saved_cpsr.it2 = it.top6;
     saved_cpsr.it1 = it.bottom2;
@@ -578,10 +583,10 @@
     tc->setMiscReg(MISCREG_LOCKFLAG, 0);

     if (cpsr.mode == MODE_HYP) {
-        tc->setMiscReg(MISCREG_ELR_HYP, curPc +
+        tc->setMiscReg(MISCREG_ELR_HYP, cur_pc +
                 (saved_cpsr.t ? thumbPcOffset(true)  : armPcOffset(true)));
     } else {
-        tc->setIntReg(INTREG_LR, curPc +
+        tc->setIntReg(INTREG_LR, cur_pc +
                 (saved_cpsr.t ? thumbPcOffset(false) :  
armPcOffset(false)));
     }

@@ -616,12 +621,12 @@
         panic("unknown Mode\n");
     }

-    Addr newPc = getVector(tc);
+    Addr new_pc = getVector(tc);
     DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x "
-            "%s\n", name(), cpsr, curPc, tc->readIntReg(INTREG_LR),
-            newPc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) :
+            "%s\n", name(), cpsr, cur_pc, tc->readIntReg(INTREG_LR),
+            new_pc, arm_inst ? csprintf("inst: %#x",  
arm_inst->encoding()) :
             std::string());
-    PCState pc(newPc);
+    PCState pc(new_pc);
     pc.thumb(cpsr.t);
     pc.nextThumb(pc.thumb());
     pc.jazelle(cpsr.j);
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 6d5411f..139d477 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -226,6 +226,8 @@

     void invoke(ThreadContext *tc, const StaticInstPtr &inst =
                 nullStaticInstPtr) override;
+    void invoke32(ThreadContext *tc, const StaticInstPtr &inst =
+                  nullStaticInstPtr);
     void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
                   nullStaticInstPtr);
     void update(ThreadContext *tc);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I244e69eee684b9935bea49cf28c6ed99a01192bf
Gerrit-Change-Number: 50507
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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