Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49690 )
Change subject: python: Move the components lib to be compiled in the binary
......................................................................
python: Move the components lib to be compiled in the binary
There has been some debate on how best to distribute the components
library. This change builds the components library into the gem5 binary.
The components library will now function similar to the `m5` library.
There is no need for awkward imports or obtaining the library from some
third-party source.
Additional incorporated in this patch:
* Added `__init__.py` to the Python modules.
* Fixed a typo in the `abstract_ruby_cache_hierarchy.py` filename.
* Ensured that imports within the library are relative.
Issue-on: https://gem5.atlassian.net/browse/GEM5-1023
Change-Id: I3988c8710cda8dcf7b21109a2cf5c3f1608cc71a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49690
Reviewed-by: Jason Lowe-Power <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Reviewed-by: Austin Harris <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M configs/example/components-library/riscv_fs.py
M src/python/SConscript
R src/python/components_library/README.md
R src/python/components_library/__init__.py
C src/python/components_library/boards/__init__.py
R src/python/components_library/boards/abstract_board.py
R src/python/components_library/boards/mem_mode.py
R src/python/components_library/boards/riscv_board.py
R src/python/components_library/boards/simple_board.py
R src/python/components_library/boards/test_board.py
R src/python/components_library/boards/x86_board.py
C src/python/components_library/cachehierarchies/__init__.py
R src/python/components_library/cachehierarchies/abstract_cache_hierarchy.py
R
src/python/components_library/cachehierarchies/abstract_two_level_cache_hierarchy.py
C src/python/components_library/cachehierarchies/classic/__init__.py
R
src/python/components_library/cachehierarchies/classic/abstract_classic_cache_hierarchy.py
C src/python/components_library/cachehierarchies/classic/caches/__init__.py
R src/python/components_library/cachehierarchies/classic/caches/l1dcache.py
R src/python/components_library/cachehierarchies/classic/caches/l1icache.py
R src/python/components_library/cachehierarchies/classic/caches/l2cache.py
R src/python/components_library/cachehierarchies/classic/caches/mmu_cache.py
R src/python/components_library/cachehierarchies/classic/no_cache.py
R
src/python/components_library/cachehierarchies/classic/private_l1_cache_hierarchy.py
R
src/python/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
R src/python/components_library/cachehierarchies/ruby/__init__.py
R
src/python/components_library/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py
C src/python/components_library/cachehierarchies/ruby/caches/__init__.py
R
src/python/components_library/cachehierarchies/ruby/caches/abstract_directory.py
R
src/python/components_library/cachehierarchies/ruby/caches/abstract_dma_controller.py
R
src/python/components_library/cachehierarchies/ruby/caches/abstract_l1_cache.py
R
src/python/components_library/cachehierarchies/ruby/caches/abstract_l2_cache.py
C
src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/__init__.py
R
src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/directory.py
R
src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
R
src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
R
src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
C
src/python/components_library/cachehierarchies/ruby/caches/mi_example/__init__.py
R
src/python/components_library/cachehierarchies/ruby/caches/mi_example/directory.py
R
src/python/components_library/cachehierarchies/ruby/caches/mi_example/dma_controller.py
R
src/python/components_library/cachehierarchies/ruby/caches/mi_example/l1_cache.py
R
src/python/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
R
src/python/components_library/cachehierarchies/ruby/mi_example_cache_hierarchy.py
R src/python/components_library/cachehierarchies/ruby/topologies/__init__.py
R
src/python/components_library/cachehierarchies/ruby/topologies/simple_pt2pt.py
R src/python/components_library/coherence_protocol.py
R src/python/components_library/isas.py
C src/python/components_library/memory/__init__.py
R src/python/components_library/memory/abstract_memory_system.py
C src/python/components_library/memory/dram_interfaces/__init__.py
R src/python/components_library/memory/dram_interfaces/ddr3.py
R src/python/components_library/memory/dram_interfaces/ddr4.py
R src/python/components_library/memory/dram_interfaces/gddr.py
R src/python/components_library/memory/dram_interfaces/hbm.py
R src/python/components_library/memory/dram_interfaces/hmc.py
R src/python/components_library/memory/dram_interfaces/lpddr2.py
R src/python/components_library/memory/dram_interfaces/lpddr3.py
R src/python/components_library/memory/dram_interfaces/lpddr5.py
R src/python/components_library/memory/dram_interfaces/wideio.py
R src/python/components_library/memory/dramsim_3.py
R src/python/components_library/memory/single_channel.py
C src/python/components_library/processors/__init__.py
R src/python/components_library/processors/abstract_core.py
R src/python/components_library/processors/abstract_generator_core.py
R src/python/components_library/processors/abstract_processor.py
R src/python/components_library/processors/complex_generator.py
R src/python/components_library/processors/complex_generator_core.py
R src/python/components_library/processors/cpu_types.py
R src/python/components_library/processors/linear_generator.py
R src/python/components_library/processors/linear_generator_core.py
R src/python/components_library/processors/random_generator.py
R src/python/components_library/processors/random_generator_core.py
R src/python/components_library/processors/simple_core.py
R src/python/components_library/processors/simple_processor.py
R src/python/components_library/processors/simple_switchable_processor.py
R src/python/components_library/processors/switchable_processor.py
C src/python/components_library/resources/__init__.py
R src/python/components_library/resources/downloader.py
R src/python/components_library/resources/resource.py
R src/python/components_library/runtime.py
C src/python/components_library/utils/__init__.py
R src/python/components_library/utils/filelock.py
R src/python/components_library/utils/override.py
R src/python/components_library/utils/requires.py
M tests/gem5/configs/components-library/boot_exit_disk_run.py
M tests/gem5/configs/components-library/boot_kvm_switch_exit.py
M tests/gem5/configs/components-library/parsec_disk_run.py
M tests/gem5/configs/components-library/simple_binary_run.py
M tests/gem5/configs/components-library/simple_traffic_run.py
88 files changed, 194 insertions(+), 122 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
Austin Harris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/components-library/riscv_fs.py
b/configs/example/components-library/riscv_fs.py
index bb3b3c0..f46e36b 100644
--- a/configs/example/components-library/riscv_fs.py
+++ b/configs/example/components-library/riscv_fs.py
@@ -38,20 +38,6 @@
import m5
from m5.objects import Root
-import sys
-import os
-
-# This is a lame hack to get the imports working correctly.
-# TODO: This needs fixed.
-sys.path.append(
- os.path.join(
- os.path.dirname(os.path.abspath(__file__)),
- os.pardir,
- os.pardir,
- os.pardir,
- )
-)
-
from components_library.runtime import get_runtime_isa
from components_library.boards.riscv_board import RiscvBoard
from components_library.memory.single_channel import SingleChannelDDR3_1600
diff --git a/src/python/SConscript b/src/python/SConscript
index ddca79a..548e6f5 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -28,6 +28,168 @@
Import('*')
+PySource('components_library', 'components_library/__init__.py')
+PySource('components_library', 'components_library/coherence_protocol.py')
+PySource('components_library', 'components_library/isas.py')
+PySource('components_library', 'components_library/runtime.py')
+PySource('components_library.boards', 'components_library/boards/__init__.py')
+PySource('components_library.boards',
+ 'components_library/boards/abstract_board.py')
+PySource('components_library.boards',
+ 'components_library/boards/mem_mode.py')
+PySource('components_library.boards',
+ 'components_library/boards/riscv_board.py')
+PySource('components_library.boards',
+ 'components_library/boards/simple_board.py')
+PySource('components_library.boards',
+ 'components_library/boards/test_board.py')
+PySource('components_library.boards', 'components_library/boards/x86_board.py')
+PySource('components_library.cachehierarchies',
+ 'components_library/cachehierarchies/__init__.py')
+PySource('components_library.cachehierarchies',
+ 'components_library/cachehierarchies/abstract_cache_hierarchy.py')
+PySource('components_library.cachehierarchies',
+ 'components_library/cachehierarchies/'
+ 'abstract_two_level_cache_hierarchy.py')
+PySource('components_library.cachehierarchies.classic',
+ 'components_library/cachehierarchies/classic/__init__.py')
+PySource('components_library.cachehierarchies.classic',
+ 'components_library/cachehierarchies/classic/'
+ 'abstract_classic_cache_hierarchy.py')
+PySource('components_library.cachehierarchies.classic',
+ 'components_library/cachehierarchies/classic/no_cache.py')
+PySource('components_library.cachehierarchies.classic',
+ 'components_library/cachehierarchies/classic/'
+ 'private_l1_cache_hierarchy.py')
+PySource('components_library.cachehierarchies.classic',
+ 'components_library/cachehierarchies/classic/'
+ 'private_l1_private_l2_cache_hierarchy.py')
+PySource('components_library.cachehierarchies.classic.caches',
+ 'components_library/cachehierarchies/classic/caches/__init__.py')
+PySource('components_library.cachehierarchies.classic.caches',
+ 'components_library/cachehierarchies/classic/caches/l1dcache.py')
+PySource('components_library.cachehierarchies.classic.caches',
+ 'components_library/cachehierarchies/classic/caches/l1icache.py')
+PySource('components_library.cachehierarchies.classic.caches',
+ 'components_library/cachehierarchies/classic/caches/l2cache.py')
+PySource('components_library.cachehierarchies.classic.caches',
+ 'components_library/cachehierarchies/classic/caches/mmu_cache.py')
+PySource('components_library.cachehierarchies.ruby',
+ 'components_library/cachehierarchies/ruby/__init__.py')
+PySource('components_library.cachehierarchies.ruby',
+ 'components_library/cachehierarchies/ruby/'
+ 'abstract_ruby_cache_hierarchy.py')
+PySource('components_library.cachehierarchies.ruby',
+ 'components_library/cachehierarchies/ruby/'
+ 'mesi_two_level_cache_hierarchy.py')
+PySource('components_library.cachehierarchies.ruby',
+ 'components_library/cachehierarchies/ruby/mi_example_cache_hierarchy.py')
+PySource('components_library.cachehierarchies.ruby.caches',
+ 'components_library/cachehierarchies/ruby/caches/__init__.py')
+PySource('components_library.cachehierarchies.ruby.caches',
+ 'components_library/cachehierarchies/ruby/caches/abstract_directory.py')
+PySource('components_library.cachehierarchies.ruby.caches',
+ 'components_library/cachehierarchies/ruby/caches/'
+ 'abstract_dma_controller.py')
+PySource('components_library.cachehierarchies.ruby.caches',
+ 'components_library/cachehierarchies/ruby/caches/abstract_l1_cache.py')
+PySource('components_library.cachehierarchies.ruby.caches',
+ 'components_library/cachehierarchies/ruby/caches/abstract_l2_cache.py')
+PySource('components_library.cachehierarchies.ruby.caches.mesi_two_level',
+ 'components_library/cachehierarchies/ruby/caches/mesi_two_level/'
+ '__init__.py')
+PySource('components_library.cachehierarchies.ruby.caches.mesi_two_level',
+ 'components_library/cachehierarchies/ruby/caches/mesi_two_level/'
+ 'directory.py')
+PySource('components_library.cachehierarchies.ruby.caches.mesi_two_level',
+ 'components_library/cachehierarchies/ruby/caches/mesi_two_level/'
+ 'dma_controller.py')
+PySource('components_library.cachehierarchies.ruby.caches.mesi_two_level',
+ 'components_library/cachehierarchies/ruby/caches/mesi_two_level/'
+ 'l1_cache.py')
+PySource('components_library.cachehierarchies.ruby.caches.mesi_two_level',
+ 'components_library/cachehierarchies/ruby/caches/mesi_two_level/'
+ 'l2_cache.py')
+PySource('components_library.cachehierarchies.ruby.caches.mi_example',
+ 'components_library/cachehierarchies/ruby/caches/mi_example/__init__.py')
+PySource('components_library.cachehierarchies.ruby.caches.mi_example',
+ 'components_library/cachehierarchies/ruby/caches/mi_example/directory.py')
+PySource('components_library.cachehierarchies.ruby.caches.mi_example',
+ 'components_library/cachehierarchies/ruby/caches/mi_example/'
+ 'dma_controller.py')
+PySource('components_library.cachehierarchies.ruby.caches.mi_example',
+ 'components_library/cachehierarchies/ruby/caches/mi_example/l1_cache.py')
+PySource('components_library.cachehierarchies.ruby.topologies',
+ 'components_library/cachehierarchies/ruby/topologies/__init__.py')
+PySource('components_library.cachehierarchies.ruby.topologies',
+ 'components_library/cachehierarchies/ruby/topologies/simple_pt2pt.py')
+PySource('components_library.memory', 'components_library/memory/__init__.py')
+PySource('components_library.memory',
+ 'components_library/memory/abstract_memory_system.py')
+PySource('components_library.memory', 'components_library/memory/dramsim_3.py')
+PySource('components_library.memory',
+ 'components_library/memory/single_channel.py')
+PySource('components_library.memory.dram_interfaces',
+ 'components_library/memory/dram_interfaces/__init__.py')
+PySource('components_library.memory.dram_interfaces',
+ 'components_library/memory/dram_interfaces/ddr3.py')
+PySource('components_library.memory.dram_interfaces',
+ 'components_library/memory/dram_interfaces/ddr4.py')
+PySource('components_library.memory.dram_interfaces',
+ 'components_library/memory/dram_interfaces/gddr.py')
+PySource('components_library.memory.dram_interfaces',
+ 'components_library/memory/dram_interfaces/hbm.py')
+PySource('components_library.memory.dram_interfaces',
+ 'components_library/memory/dram_interfaces/hmc.py')
+PySource('components_library.memory.dram_interfaces',
+ 'components_library/memory/dram_interfaces/lpddr2.py')
+PySource('components_library.memory.dram_interfaces',
+ 'components_library/memory/dram_interfaces/lpddr3.py')
+PySource('components_library.memory.dram_interfaces',
+ 'components_library/memory/dram_interfaces/lpddr5.py')
+PySource('components_library.memory.dram_interfaces',
+ 'components_library/memory/dram_interfaces/wideio.py')
+PySource('components_library.processors',
+ 'components_library/processors/__init__.py')
+PySource('components_library.processors',
+ 'components_library/processors/abstract_core.py')
+PySource('components_library.processors',
+ 'components_library/processors/abstract_generator_core.py')
+PySource('components_library.processors',
+ 'components_library/processors/abstract_processor.py')
+PySource('components_library.processors',
+ 'components_library/processors/complex_generator_core.py')
+PySource('components_library.processors',
+ 'components_library/processors/complex_generator.py')
+PySource('components_library.processors',
+ 'components_library/processors/cpu_types.py')
+PySource('components_library.processors',
+ 'components_library/processors/linear_generator_core.py')
+PySource('components_library.processors',
+ 'components_library/processors/linear_generator.py')
+PySource('components_library.processors',
+ 'components_library/processors/random_generator_core.py')
+PySource('components_library.processors',
+ 'components_library/processors/random_generator.py')
+PySource('components_library.processors',
+ 'components_library/processors/simple_core.py')
+PySource('components_library.processors',
+ 'components_library/processors/simple_processor.py')
+PySource('components_library.processors',
+ 'components_library/processors/simple_switchable_processor.py')
+PySource('components_library.processors',
+ 'components_library/processors/switchable_processor.py')
+PySource('components_library.resources',
+ 'components_library/resources/__init__.py')
+PySource('components_library.resources',
+ 'components_library/resources/downloader.py')
+PySource('components_library.resources',
+ 'components_library/resources/resource.py')
+PySource('components_library.utils', 'components_library/utils/__init__.py')
+PySource('components_library.utils', 'components_library/utils/filelock.py')
+PySource('components_library.utils', 'components_library/utils/override.py')
+PySource('components_library.utils', 'components_library/utils/requires.py')
+
PySource('', 'importer.py')
PySource('m5', 'm5/__init__.py')
PySource('m5', 'm5/SimObject.py')
diff --git a/components_library/README.md
b/src/python/components_library/README.md
similarity index 100%
rename from components_library/README.md
rename to src/python/components_library/README.md
diff --git a/components_library/__init__.py
b/src/python/components_library/__init__.py
similarity index 100%
rename from components_library/__init__.py
rename to src/python/components_library/__init__.py
diff --git a/components_library/__init__.py
b/src/python/components_library/boards/__init__.py
similarity index 100%
copy from components_library/__init__.py
copy to src/python/components_library/boards/__init__.py
diff --git a/components_library/boards/abstract_board.py
b/src/python/components_library/boards/abstract_board.py
similarity index 100%
rename from components_library/boards/abstract_board.py
rename to src/python/components_library/boards/abstract_board.py
diff --git a/components_library/boards/mem_mode.py
b/src/python/components_library/boards/mem_mode.py
similarity index 100%
rename from components_library/boards/mem_mode.py
rename to src/python/components_library/boards/mem_mode.py
diff --git a/components_library/boards/riscv_board.py
b/src/python/components_library/boards/riscv_board.py
similarity index 100%
rename from components_library/boards/riscv_board.py
rename to src/python/components_library/boards/riscv_board.py
diff --git a/components_library/boards/simple_board.py
b/src/python/components_library/boards/simple_board.py
similarity index 98%
rename from components_library/boards/simple_board.py
rename to src/python/components_library/boards/simple_board.py
index 86e6890..0ff9b79 100644
--- a/components_library/boards/simple_board.py
+++ b/src/python/components_library/boards/simple_board.py
@@ -24,7 +24,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from components_library.resources.resource import AbstractResource
+from ..resources.resource import AbstractResource
from m5.objects import (
AddrRange,
SrcClockDomain,
diff --git a/components_library/boards/test_board.py
b/src/python/components_library/boards/test_board.py
similarity index 100%
rename from components_library/boards/test_board.py
rename to src/python/components_library/boards/test_board.py
diff --git a/components_library/boards/x86_board.py
b/src/python/components_library/boards/x86_board.py
similarity index 97%
rename from components_library/boards/x86_board.py
rename to src/python/components_library/boards/x86_board.py
index 3f184b6..f752037 100644
--- a/components_library/boards/x86_board.py
+++ b/src/python/components_library/boards/x86_board.py
@@ -25,10 +25,10 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from components_library.resources.resource import AbstractResource
-from components_library.utils.override import overrides
-from components_library.boards.abstract_board import AbstractBoard
-from components_library.isas import ISA
+from ..resources.resource import AbstractResource
+from ..utils.override import overrides
+from .abstract_board import AbstractBoard
+from ..isas import ISA
import m5
from m5.objects import (
diff --git
a/components_library/cachehierarchies/ruby/topologies/__init__.py
b/src/python/components_library/cachehierarchies/__init__.py
similarity index 100%
copy from components_library/cachehierarchies/ruby/topologies/__init__.py
copy to src/python/components_library/cachehierarchies/__init__.py
diff --git
a/components_library/cachehierarchies/abstract_cache_hierarchy.py
b/src/python/components_library/cachehierarchies/abstract_cache_hierarchy.py
similarity index 100%
rename from components_library/cachehierarchies/abstract_cache_hierarchy.py
rename to
src/python/components_library/cachehierarchies/abstract_cache_hierarchy.py
diff --git
a/components_library/cachehierarchies/abstract_two_level_cache_hierarchy.py
b/src/python/components_library/cachehierarchies/abstract_two_level_cache_hierarchy.py
similarity index 100%
rename from
components_library/cachehierarchies/abstract_two_level_cache_hierarchy.py
rename to
src/python/components_library/cachehierarchies/abstract_two_level_cache_hierarchy.py
diff --git a/components_library/__init__.py
b/src/python/components_library/cachehierarchies/classic/__init__.py
similarity index 100%
copy from components_library/__init__.py
copy to src/python/components_library/cachehierarchies/classic/__init__.py
diff --git
a/components_library/cachehierarchies/classic/abstract_classic_cache_hierarchy.py
b/src/python/components_library/cachehierarchies/classic/abstract_classic_cache_hierarchy.py
similarity index 100%
rename from
components_library/cachehierarchies/classic/abstract_classic_cache_hierarchy.py
rename to
src/python/components_library/cachehierarchies/classic/abstract_classic_cache_hierarchy.py
diff --git
a/components_library/cachehierarchies/ruby/topologies/__init__.py
b/src/python/components_library/cachehierarchies/classic/caches/__init__.py
similarity index 100%
copy from components_library/cachehierarchies/ruby/topologies/__init__.py
copy to
src/python/components_library/cachehierarchies/classic/caches/__init__.py
diff --git a/components_library/cachehierarchies/classic/caches/l1dcache.py
b/src/python/components_library/cachehierarchies/classic/caches/l1dcache.py
similarity index 100%
rename from components_library/cachehierarchies/classic/caches/l1dcache.py
rename to
src/python/components_library/cachehierarchies/classic/caches/l1dcache.py
diff --git a/components_library/cachehierarchies/classic/caches/l1icache.py
b/src/python/components_library/cachehierarchies/classic/caches/l1icache.py
similarity index 100%
rename from components_library/cachehierarchies/classic/caches/l1icache.py
rename to
src/python/components_library/cachehierarchies/classic/caches/l1icache.py
diff --git a/components_library/cachehierarchies/classic/caches/l2cache.py
b/src/python/components_library/cachehierarchies/classic/caches/l2cache.py
similarity index 100%
rename from components_library/cachehierarchies/classic/caches/l2cache.py
rename to
src/python/components_library/cachehierarchies/classic/caches/l2cache.py
diff --git
a/components_library/cachehierarchies/classic/caches/mmu_cache.py
b/src/python/components_library/cachehierarchies/classic/caches/mmu_cache.py
similarity index 100%
rename from components_library/cachehierarchies/classic/caches/mmu_cache.py
rename to
src/python/components_library/cachehierarchies/classic/caches/mmu_cache.py
diff --git a/components_library/cachehierarchies/classic/no_cache.py
b/src/python/components_library/cachehierarchies/classic/no_cache.py
similarity index 97%
rename from components_library/cachehierarchies/classic/no_cache.py
rename to src/python/components_library/cachehierarchies/classic/no_cache.py
index 106b74f..83a2dc8 100644
--- a/components_library/cachehierarchies/classic/no_cache.py
+++ b/src/python/components_library/cachehierarchies/classic/no_cache.py
@@ -24,10 +24,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from components_library.cachehierarchies.classic.\
- abstract_classic_cache_hierarchy import (
- AbstractClassicCacheHierarchy,
-)
+from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy
from ..abstract_cache_hierarchy import AbstractCacheHierarchy
from ...boards.abstract_board import AbstractBoard
from ...isas import ISA
diff --git
a/components_library/cachehierarchies/classic/private_l1_cache_hierarchy.py
b/src/python/components_library/cachehierarchies/classic/private_l1_cache_hierarchy.py
similarity index 100%
rename from
components_library/cachehierarchies/classic/private_l1_cache_hierarchy.py
rename to
src/python/components_library/cachehierarchies/classic/private_l1_cache_hierarchy.py
diff --git
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
b/src/python/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
similarity index 100%
rename from
components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
rename to
src/python/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
diff --git a/components_library/cachehierarchies/ruby/__init__.py
b/src/python/components_library/cachehierarchies/ruby/__init__.py
similarity index 100%
rename from components_library/cachehierarchies/ruby/__init__.py
rename to src/python/components_library/cachehierarchies/ruby/__init__.py
diff --git
a/components_library/cachehierarchies/ruby/abstract_ruby_cache_hierarhcy.py
b/src/python/components_library/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py
similarity index 96%
rename from
components_library/cachehierarchies/ruby/abstract_ruby_cache_hierarhcy.py
rename to
src/python/components_library/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py
index 1b9a7c7..679d1a7 100644
---
a/components_library/cachehierarchies/ruby/abstract_ruby_cache_hierarhcy.py
+++
b/src/python/components_library/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py
@@ -24,7 +24,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from components_library.utils.override import overrides
+from ...utils.override import overrides
from ..abstract_cache_hierarchy import AbstractCacheHierarchy
diff --git
a/components_library/cachehierarchies/ruby/topologies/__init__.py
b/src/python/components_library/cachehierarchies/ruby/caches/__init__.py
similarity index 100%
copy from components_library/cachehierarchies/ruby/topologies/__init__.py
copy to
src/python/components_library/cachehierarchies/ruby/caches/__init__.py
diff --git
a/components_library/cachehierarchies/ruby/caches/abstract_directory.py
b/src/python/components_library/cachehierarchies/ruby/caches/abstract_directory.py
similarity index 100%
rename from
components_library/cachehierarchies/ruby/caches/abstract_directory.py
rename to
src/python/components_library/cachehierarchies/ruby/caches/abstract_directory.py
diff --git
a/components_library/cachehierarchies/ruby/caches/abstract_dma_controller.py
b/src/python/components_library/cachehierarchies/ruby/caches/abstract_dma_controller.py
similarity index 100%
rename from
components_library/cachehierarchies/ruby/caches/abstract_dma_controller.py
rename to
src/python/components_library/cachehierarchies/ruby/caches/abstract_dma_controller.py
diff --git
a/components_library/cachehierarchies/ruby/caches/abstract_l1_cache.py
b/src/python/components_library/cachehierarchies/ruby/caches/abstract_l1_cache.py
similarity index 94%
rename from
components_library/cachehierarchies/ruby/caches/abstract_l1_cache.py
rename to
src/python/components_library/cachehierarchies/ruby/caches/abstract_l1_cache.py
index 265423c..e694194 100644
--- a/components_library/cachehierarchies/ruby/caches/abstract_l1_cache.py
+++
b/src/python/components_library/cachehierarchies/ruby/caches/abstract_l1_cache.py
@@ -25,9 +25,9 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from abc import abstractmethod
-from components_library.isas import ISA
-from components_library.processors.cpu_types import CPUTypes
-from components_library.processors.abstract_core import AbstractCore
+from ....isas import ISA
+from ....processors.cpu_types import CPUTypes
+from ....processors.abstract_core import AbstractCore
from m5.objects import L1Cache_Controller
diff --git
a/components_library/cachehierarchies/ruby/caches/abstract_l2_cache.py
b/src/python/components_library/cachehierarchies/ruby/caches/abstract_l2_cache.py
similarity index 100%
rename from
components_library/cachehierarchies/ruby/caches/abstract_l2_cache.py
rename to
src/python/components_library/cachehierarchies/ruby/caches/abstract_l2_cache.py
diff --git a/components_library/__init__.py
b/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/__init__.py
similarity index 100%
copy from components_library/__init__.py
copy to
src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/__init__.py
diff --git
a/components_library/cachehierarchies/ruby/caches/mesi_two_level/directory.py
b/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/directory.py
similarity index 97%
rename from
components_library/cachehierarchies/ruby/caches/mesi_two_level/directory.py
rename to
src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/directory.py
index 8534bf6..1825765 100644
---
a/components_library/cachehierarchies/ruby/caches/mesi_two_level/directory.py
+++
b/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/directory.py
@@ -24,7 +24,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from components_library.utils.override import overrides
+from .....utils.override import overrides
from ..abstract_directory import AbstractDirectory
from m5.objects import (
diff --git
a/components_library/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
b/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
similarity index 97%
rename from
components_library/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
rename to
src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
index d4b1c78..c37d4ef 100644
---
a/components_library/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
+++
b/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
@@ -24,7 +24,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from components_library.utils.override import overrides
+from .....utils.override import overrides
from ..abstract_dma_controller import AbstractDMAController
from m5.objects import MessageBuffer
diff --git
a/components_library/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
b/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
similarity index 95%
rename from
components_library/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
rename to
src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
index a85b864..ab04d47 100644
---
a/components_library/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
+++
b/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
@@ -24,10 +24,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from components_library.processors.abstract_core import AbstractCore
-from components_library.isas import ISA
+from .....processors.abstract_core import AbstractCore
+from .....isas import ISA
from ..abstract_l1_cache import AbstractL1Cache
-from components_library.utils.override import *
+from .....utils.override import *
from m5.objects import (
MessageBuffer,
diff --git
a/components_library/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
b/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
similarity index 98%
rename from
components_library/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
rename to
src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
index 2c8bc5d..43f675e 100644
---
a/components_library/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
+++
b/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
@@ -25,7 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from ..abstract_l2_cache import AbstractL2Cache
-from components_library.utils.override import *
+from .....utils.override import *
from m5.objects import MessageBuffer, RubyCache
diff --git a/components_library/__init__.py
b/src/python/components_library/cachehierarchies/ruby/caches/mi_example/__init__.py
similarity index 100%
copy from components_library/__init__.py
copy to
src/python/components_library/cachehierarchies/ruby/caches/mi_example/__init__.py
diff --git
a/components_library/cachehierarchies/ruby/caches/mi_example/directory.py
b/src/python/components_library/cachehierarchies/ruby/caches/mi_example/directory.py
similarity index 100%
rename from
components_library/cachehierarchies/ruby/caches/mi_example/directory.py
rename to
src/python/components_library/cachehierarchies/ruby/caches/mi_example/directory.py
diff --git
a/components_library/cachehierarchies/ruby/caches/mi_example/dma_controller.py
b/src/python/components_library/cachehierarchies/ruby/caches/mi_example/dma_controller.py
similarity index 100%
rename from
components_library/cachehierarchies/ruby/caches/mi_example/dma_controller.py
rename to
src/python/components_library/cachehierarchies/ruby/caches/mi_example/dma_controller.py
diff --git
a/components_library/cachehierarchies/ruby/caches/mi_example/l1_cache.py
b/src/python/components_library/cachehierarchies/ruby/caches/mi_example/l1_cache.py
similarity index 100%
rename from
components_library/cachehierarchies/ruby/caches/mi_example/l1_cache.py
rename to
src/python/components_library/cachehierarchies/ruby/caches/mi_example/l1_cache.py
diff --git
a/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
b/src/python/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
similarity index 98%
rename from
components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
rename to
src/python/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
index 42f1e2f..7bda49c 100644
---
a/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++
b/src/python/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
@@ -25,13 +25,13 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from .abstract_ruby_cache_hierarhcy import AbstractRubyCacheHierarchy
+from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
from ..abstract_two_level_cache_hierarchy import
AbstractTwoLevelCacheHierarchy
from ...coherence_protocol import CoherenceProtocol
from ...isas import ISA
from ...boards.abstract_board import AbstractBoard
from ...runtime import get_runtime_isa
-from components_library.utils.requires import requires
+from ...utils.requires import requires
from .topologies.simple_pt2pt import SimplePt2Pt
from .caches.mesi_two_level.l1_cache import L1Cache
diff --git
a/components_library/cachehierarchies/ruby/mi_example_cache_hierarchy.py
b/src/python/components_library/cachehierarchies/ruby/mi_example_cache_hierarchy.py
similarity index 98%
rename from
components_library/cachehierarchies/ruby/mi_example_cache_hierarchy.py
rename to
src/python/components_library/cachehierarchies/ruby/mi_example_cache_hierarchy.py
index c219e81..c5f93bd 100644
--- a/components_library/cachehierarchies/ruby/mi_example_cache_hierarchy.py
+++
b/src/python/components_library/cachehierarchies/ruby/mi_example_cache_hierarchy.py
@@ -28,14 +28,14 @@
from .caches.mi_example.dma_controller import DMAController
from .caches.mi_example.directory import Directory
from .topologies.simple_pt2pt import SimplePt2Pt
-from .abstract_ruby_cache_hierarhcy import AbstractRubyCacheHierarchy
+from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
from ..abstract_cache_hierarchy import AbstractCacheHierarchy
from ...boards.abstract_board import AbstractBoard
from ...coherence_protocol import CoherenceProtocol
from ...isas import ISA
from ...utils.override import overrides
from ...runtime import get_runtime_isa
-from components_library.utils.requires import requires
+from ...utils.requires import requires
from m5.objects import (
diff --git
a/components_library/cachehierarchies/ruby/topologies/__init__.py
b/src/python/components_library/cachehierarchies/ruby/topologies/__init__.py
similarity index 100%
rename from components_library/cachehierarchies/ruby/topologies/__init__.py
rename to
src/python/components_library/cachehierarchies/ruby/topologies/__init__.py
diff --git
a/components_library/cachehierarchies/ruby/topologies/simple_pt2pt.py
b/src/python/components_library/cachehierarchies/ruby/topologies/simple_pt2pt.py
similarity index 100%
rename from
components_library/cachehierarchies/ruby/topologies/simple_pt2pt.py
rename to
src/python/components_library/cachehierarchies/ruby/topologies/simple_pt2pt.py
diff --git a/components_library/coherence_protocol.py
b/src/python/components_library/coherence_protocol.py
similarity index 100%
rename from components_library/coherence_protocol.py
rename to src/python/components_library/coherence_protocol.py
diff --git a/components_library/isas.py
b/src/python/components_library/isas.py
similarity index 100%
rename from components_library/isas.py
rename to src/python/components_library/isas.py
diff --git a/components_library/__init__.py
b/src/python/components_library/memory/__init__.py
similarity index 100%
copy from components_library/__init__.py
copy to src/python/components_library/memory/__init__.py
diff --git a/components_library/memory/abstract_memory_system.py
b/src/python/components_library/memory/abstract_memory_system.py
similarity index 100%
rename from components_library/memory/abstract_memory_system.py
rename to src/python/components_library/memory/abstract_memory_system.py
diff --git
a/components_library/cachehierarchies/ruby/topologies/__init__.py
b/src/python/components_library/memory/dram_interfaces/__init__.py
similarity index 100%
copy from components_library/cachehierarchies/ruby/topologies/__init__.py
copy to src/python/components_library/memory/dram_interfaces/__init__.py
diff --git a/components_library/memory/dram_interfaces/ddr3.py
b/src/python/components_library/memory/dram_interfaces/ddr3.py
similarity index 100%
rename from components_library/memory/dram_interfaces/ddr3.py
rename to src/python/components_library/memory/dram_interfaces/ddr3.py
diff --git a/components_library/memory/dram_interfaces/ddr4.py
b/src/python/components_library/memory/dram_interfaces/ddr4.py
similarity index 100%
rename from components_library/memory/dram_interfaces/ddr4.py
rename to src/python/components_library/memory/dram_interfaces/ddr4.py
diff --git a/components_library/memory/dram_interfaces/gddr.py
b/src/python/components_library/memory/dram_interfaces/gddr.py
similarity index 100%
rename from components_library/memory/dram_interfaces/gddr.py
rename to src/python/components_library/memory/dram_interfaces/gddr.py
diff --git a/components_library/memory/dram_interfaces/hbm.py
b/src/python/components_library/memory/dram_interfaces/hbm.py
similarity index 100%
rename from components_library/memory/dram_interfaces/hbm.py
rename to src/python/components_library/memory/dram_interfaces/hbm.py
diff --git a/components_library/memory/dram_interfaces/hmc.py
b/src/python/components_library/memory/dram_interfaces/hmc.py
similarity index 100%
rename from components_library/memory/dram_interfaces/hmc.py
rename to src/python/components_library/memory/dram_interfaces/hmc.py
diff --git a/components_library/memory/dram_interfaces/lpddr2.py
b/src/python/components_library/memory/dram_interfaces/lpddr2.py
similarity index 100%
rename from components_library/memory/dram_interfaces/lpddr2.py
rename to src/python/components_library/memory/dram_interfaces/lpddr2.py
diff --git a/components_library/memory/dram_interfaces/lpddr3.py
b/src/python/components_library/memory/dram_interfaces/lpddr3.py
similarity index 100%
rename from components_library/memory/dram_interfaces/lpddr3.py
rename to src/python/components_library/memory/dram_interfaces/lpddr3.py
diff --git a/components_library/memory/dram_interfaces/lpddr5.py
b/src/python/components_library/memory/dram_interfaces/lpddr5.py
similarity index 100%
rename from components_library/memory/dram_interfaces/lpddr5.py
rename to src/python/components_library/memory/dram_interfaces/lpddr5.py
diff --git a/components_library/memory/dram_interfaces/wideio.py
b/src/python/components_library/memory/dram_interfaces/wideio.py
similarity index 100%
rename from components_library/memory/dram_interfaces/wideio.py
rename to src/python/components_library/memory/dram_interfaces/wideio.py
diff --git a/components_library/memory/dramsim_3.py
b/src/python/components_library/memory/dramsim_3.py
similarity index 100%
rename from components_library/memory/dramsim_3.py
rename to src/python/components_library/memory/dramsim_3.py
diff --git a/components_library/memory/single_channel.py
b/src/python/components_library/memory/single_channel.py
similarity index 100%
rename from components_library/memory/single_channel.py
rename to src/python/components_library/memory/single_channel.py
diff --git a/components_library/__init__.py
b/src/python/components_library/processors/__init__.py
similarity index 100%
copy from components_library/__init__.py
copy to src/python/components_library/processors/__init__.py
diff --git a/components_library/processors/abstract_core.py
b/src/python/components_library/processors/abstract_core.py
similarity index 100%
rename from components_library/processors/abstract_core.py
rename to src/python/components_library/processors/abstract_core.py
diff --git a/components_library/processors/abstract_generator_core.py
b/src/python/components_library/processors/abstract_generator_core.py
similarity index 100%
rename from components_library/processors/abstract_generator_core.py
rename to
src/python/components_library/processors/abstract_generator_core.py
diff --git a/components_library/processors/abstract_processor.py
b/src/python/components_library/processors/abstract_processor.py
similarity index 96%
rename from components_library/processors/abstract_processor.py
rename to src/python/components_library/processors/abstract_processor.py
index 9ee3fce..42ee194 100644
--- a/components_library/processors/abstract_processor.py
+++ b/src/python/components_library/processors/abstract_processor.py
@@ -25,7 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from abc import ABCMeta, abstractmethod
-from components_library.processors.abstract_core import AbstractCore
+from .abstract_core import AbstractCore
from m5.objects import SubSystem
diff --git a/components_library/processors/complex_generator.py
b/src/python/components_library/processors/complex_generator.py
similarity index 100%
rename from components_library/processors/complex_generator.py
rename to src/python/components_library/processors/complex_generator.py
diff --git a/components_library/processors/complex_generator_core.py
b/src/python/components_library/processors/complex_generator_core.py
similarity index 100%
rename from components_library/processors/complex_generator_core.py
rename to src/python/components_library/processors/complex_generator_core.py
diff --git a/components_library/processors/cpu_types.py
b/src/python/components_library/processors/cpu_types.py
similarity index 100%
rename from components_library/processors/cpu_types.py
rename to src/python/components_library/processors/cpu_types.py
diff --git a/components_library/processors/linear_generator.py
b/src/python/components_library/processors/linear_generator.py
similarity index 100%
rename from components_library/processors/linear_generator.py
rename to src/python/components_library/processors/linear_generator.py
diff --git a/components_library/processors/linear_generator_core.py
b/src/python/components_library/processors/linear_generator_core.py
similarity index 100%
rename from components_library/processors/linear_generator_core.py
rename to src/python/components_library/processors/linear_generator_core.py
diff --git a/components_library/processors/random_generator.py
b/src/python/components_library/processors/random_generator.py
similarity index 100%
rename from components_library/processors/random_generator.py
rename to src/python/components_library/processors/random_generator.py
diff --git a/components_library/processors/random_generator_core.py
b/src/python/components_library/processors/random_generator_core.py
similarity index 100%
rename from components_library/processors/random_generator_core.py
rename to src/python/components_library/processors/random_generator_core.py
diff --git a/components_library/processors/simple_core.py
b/src/python/components_library/processors/simple_core.py
similarity index 96%
rename from components_library/processors/simple_core.py
rename to src/python/components_library/processors/simple_core.py
index 202343d..f502e68 100644
--- a/components_library/processors/simple_core.py
+++ b/src/python/components_library/processors/simple_core.py
@@ -25,8 +25,8 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from typing import Optional
-from components_library.runtime import get_runtime_isa
-from components_library.processors.abstract_core import AbstractCore
+from ..runtime import get_runtime_isa
+from ..processors.abstract_core import AbstractCore
from .cpu_types import CPUTypes
from ..isas import ISA
diff --git a/components_library/processors/simple_processor.py
b/src/python/components_library/processors/simple_processor.py
similarity index 95%
rename from components_library/processors/simple_processor.py
rename to src/python/components_library/processors/simple_processor.py
index 1eac24a..d264034 100644
--- a/components_library/processors/simple_processor.py
+++ b/src/python/components_library/processors/simple_processor.py
@@ -25,9 +25,9 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from components_library.utils.override import overrides
-from components_library.boards.mem_mode import MemMode
-from components_library.processors.simple_core import SimpleCore
+from ..utils.override import overrides
+from ..boards.mem_mode import MemMode
+from ..processors.simple_core import SimpleCore
from m5.util import warn
diff --git a/components_library/processors/simple_switchable_processor.py
b/src/python/components_library/processors/simple_switchable_processor.py
similarity index 93%
rename from components_library/processors/simple_switchable_processor.py
rename to
src/python/components_library/processors/simple_switchable_processor.py
index a875817..9d69588 100644
--- a/components_library/processors/simple_switchable_processor.py
+++
b/src/python/components_library/processors/simple_switchable_processor.py
@@ -24,10 +24,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from components_library.boards.mem_mode import MemMode
-from components_library.boards.abstract_board import AbstractBoard
-from components_library.processors.simple_core import SimpleCore
-from components_library.processors.cpu_types import CPUTypes
+from ..boards.mem_mode import MemMode
+from ..boards.abstract_board import AbstractBoard
+from ..processors.simple_core import SimpleCore
+from ..processors.cpu_types import CPUTypes
from .switchable_processor import SwitchableProcessor
from ..utils.override import *
diff --git a/components_library/processors/switchable_processor.py
b/src/python/components_library/processors/switchable_processor.py
similarity index 97%
rename from components_library/processors/switchable_processor.py
rename to src/python/components_library/processors/switchable_processor.py
index 3495a27..772304b 100644
--- a/components_library/processors/switchable_processor.py
+++ b/src/python/components_library/processors/switchable_processor.py
@@ -24,9 +24,9 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from components_library.processors.simple_core import SimpleCore
-from components_library.processors.abstract_core import AbstractCore
+from .simple_core import SimpleCore
+from .abstract_core import AbstractCore
from .cpu_types import CPUTypes
import m5
diff --git
a/components_library/cachehierarchies/ruby/topologies/__init__.py
b/src/python/components_library/resources/__init__.py
similarity index 100%
copy from components_library/cachehierarchies/ruby/topologies/__init__.py
copy to src/python/components_library/resources/__init__.py
diff --git a/components_library/resources/downloader.py
b/src/python/components_library/resources/downloader.py
similarity index 100%
rename from components_library/resources/downloader.py
rename to src/python/components_library/resources/downloader.py
diff --git a/components_library/resources/resource.py
b/src/python/components_library/resources/resource.py
similarity index 100%
rename from components_library/resources/resource.py
rename to src/python/components_library/resources/resource.py
diff --git a/components_library/runtime.py
b/src/python/components_library/runtime.py
similarity index 100%
rename from components_library/runtime.py
rename to src/python/components_library/runtime.py
diff --git a/components_library/__init__.py
b/src/python/components_library/utils/__init__.py
similarity index 100%
copy from components_library/__init__.py
copy to src/python/components_library/utils/__init__.py
diff --git a/components_library/utils/filelock.py
b/src/python/components_library/utils/filelock.py
similarity index 100%
rename from components_library/utils/filelock.py
rename to src/python/components_library/utils/filelock.py
diff --git a/components_library/utils/override.py
b/src/python/components_library/utils/override.py
similarity index 100%
rename from components_library/utils/override.py
rename to src/python/components_library/utils/override.py
diff --git a/components_library/utils/requires.py
b/src/python/components_library/utils/requires.py
similarity index 100%
rename from components_library/utils/requires.py
rename to src/python/components_library/utils/requires.py
diff --git a/tests/gem5/configs/components-library/boot_exit_disk_run.py
b/tests/gem5/configs/components-library/boot_exit_disk_run.py
index 48b4d93..015d84e 100644
--- a/tests/gem5/configs/components-library/boot_exit_disk_run.py
+++ b/tests/gem5/configs/components-library/boot_exit_disk_run.py
@@ -31,21 +31,6 @@
import m5
from m5.objects import Root
-import sys
-import os
-
-# This is a lame hack to get the imports working correctly.
-# TODO: This needs fixed.
-sys.path.append(
- os.path.join(
- os.path.dirname(os.path.abspath(__file__)),
- os.pardir,
- os.pardir,
- os.pardir,
- os.pardir,
- )
-)
-
from components_library.runtime import (
get_runtime_coherence_protocol,
get_runtime_isa,
@@ -59,7 +44,6 @@
from components_library.coherence_protocol import CoherenceProtocol
from components_library.resources.resource import Resource
-import os
import argparse
parser = argparse.ArgumentParser(
diff --git a/tests/gem5/configs/components-library/boot_kvm_switch_exit.py
b/tests/gem5/configs/components-library/boot_kvm_switch_exit.py
index d508e04..28102d8 100644
--- a/tests/gem5/configs/components-library/boot_kvm_switch_exit.py
+++ b/tests/gem5/configs/components-library/boot_kvm_switch_exit.py
@@ -29,24 +29,10 @@
"""
import argparse
-import os
-import sys
import m5
from m5.objects import Root
-# This is a lame hack to get the imports working correctly.
-# TODO: This needs fixed.
-sys.path.append(
- os.path.join(
- os.path.dirname(os.path.abspath(__file__)),
- os.pardir,
- os.pardir,
- os.pardir,
- os.pardir,
- )
-)
-
from components_library.boards.x86_board import X86Board
from components_library.coherence_protocol import CoherenceProtocol
from components_library.isas import ISA
diff --git a/tests/gem5/configs/components-library/parsec_disk_run.py
b/tests/gem5/configs/components-library/parsec_disk_run.py
index 8868652..31df0bf 100644
--- a/tests/gem5/configs/components-library/parsec_disk_run.py
+++ b/tests/gem5/configs/components-library/parsec_disk_run.py
@@ -39,20 +39,6 @@
import m5.ticks
from m5.objects import Root
-import sys
-import os
-
-# This is a lame hack to get the imports working correctly.
-# TODO: This needs fixed.
-sys.path.append(
- os.path.join(
- os.path.dirname(os.path.abspath(__file__)),
- os.pardir,
- os.pardir,
- os.pardir,
- os.pardir,
- )
-)
from components_library.resources.resource import Resource
from components_library.boards.x86_board import X86Board
diff --git a/tests/gem5/configs/components-library/simple_binary_run.py
b/tests/gem5/configs/components-library/simple_binary_run.py
index 6c7e590..9ed889d 100644
--- a/tests/gem5/configs/components-library/simple_binary_run.py
+++ b/tests/gem5/configs/components-library/simple_binary_run.py
@@ -33,21 +33,6 @@
import m5
from m5.objects import Root
-import os
-import sys
-
-# This is a lame hack to get the imports working correctly.
-# TODO: This needs fixed.
-sys.path.append(
- os.path.join(
- os.path.dirname(os.path.abspath(__file__)),
- os.pardir,
- os.pardir,
- os.pardir,
- os.pardir,
- )
-)
-
from components_library.resources.resource import Resource
from components_library.boards.simple_board import SimpleBoard
from components_library.cachehierarchies.classic.no_cache import NoCache
diff --git a/tests/gem5/configs/components-library/simple_traffic_run.py
b/tests/gem5/configs/components-library/simple_traffic_run.py
index b2a168c..4b2e99a 100644
--- a/tests/gem5/configs/components-library/simple_traffic_run.py
+++ b/tests/gem5/configs/components-library/simple_traffic_run.py
@@ -34,23 +34,9 @@
from m5.objects import Root
-import sys
-import os
import argparse
import importlib
-# This is a lame hack to get the imports working correctly.
-# TODO: This needs fixed.
-sys.path.append(
- os.path.join(
- os.path.dirname(os.path.abspath(__file__)),
- os.pardir,
- os.pardir,
- os.pardir,
- os.pardir,
- )
-)
-
from components_library.boards.test_board import TestBoard
from components_library.cachehierarchies.classic.no_cache import NoCache
from components_library.memory.single_channel import *
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49690
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https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3988c8710cda8dcf7b21109a2cf5c3f1608cc71a
Gerrit-Change-Number: 49690
Gerrit-PatchSet: 21
Gerrit-Owner: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Austin Harris <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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