Tom Rollet has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50729 )
Change subject: cpu-o3: replace 'loads' counter per loadQueue.size()
......................................................................
cpu-o3: replace 'loads' counter per loadQueue.size()
Change-Id: Id65776b385f571e4e325b0ffa022bfa765c224bf
---
M src/cpu/o3/lsq_unit.cc
M src/cpu/o3/lsq_unit.hh
2 files changed, 13 insertions(+), 21 deletions(-)
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 34f65b9..b4f8477 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -202,7 +202,7 @@
LSQUnit::LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
: lsqID(-1), storeQueue(sqEntries+1), loadQueue(lqEntries+1),
- loads(0), stores(0), storesToWB(0),
+ stores(0), storesToWB(0),
htmStarts(0), htmStops(0),
lastRetiredHtmUid(0),
cacheBlockMask(0), stalled(false),
@@ -236,7 +236,7 @@
void
LSQUnit::resetState()
{
- loads = stores = storesToWB = 0;
+ stores = storesToWB = 0;
// hardware transactional memory
// nesting depth
@@ -330,7 +330,7 @@
LSQUnit::insertLoad(const DynInstPtr &load_inst)
{
assert(!loadQueue.full());
- assert(loads < loadQueue.capacity());
+ assert(loadQueue.size() < loadQueue.capacity());
DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
load_inst->pcState(), loadQueue.tail(), load_inst->seqNum);
@@ -346,8 +346,6 @@
assert(load_inst->lqIdx > 0);
load_inst->lqIt = loadQueue.getIterator(load_inst->lqIdx);
- ++loads;
-
// hardware transactional memory
// transactional state and nesting depth must be tracked
// in the in-order part of the core.
@@ -425,8 +423,8 @@
//LQ has an extra dummy entry to differentiate
//empty/full conditions. Subtract 1 from the free entries.
DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n",
- 1 + loadQueue.capacity(), loads);
- return loadQueue.capacity() - loads;
+ 1 + loadQueue.capacity(), loadQueue.size());
+ return loadQueue.capacity() - loadQueue.size();
}
unsigned
@@ -749,16 +747,14 @@
loadQueue.front().clear();
loadQueue.pop_front();
-
- --loads;
}
void
LSQUnit::commitLoads(InstSeqNum &youngest_inst)
{
- assert(loads == 0 || loadQueue.front().valid());
+ assert(loadQueue.size() == 0 || loadQueue.front().valid());
- while (loads != 0 && loadQueue.front().instruction()->seqNum
+ while (loadQueue.size() != 0 && loadQueue.front().instruction()->seqNum
<= youngest_inst) {
commitLoad();
}
@@ -949,9 +945,9 @@
LSQUnit::squash(const InstSeqNum &squashed_num)
{
DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
- "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
+ "(Loads:%i Stores:%i)\n", squashed_num, loadQueue.size(),
stores);
- while (loads != 0 &&
+ while (loadQueue.size() != 0 &&
loadQueue.back().instruction()->seqNum > squashed_num) {
DPRINTF(LSQUnit,"Load Instruction PC %s squashed, "
"[sn:%lli]\n",
@@ -983,8 +979,6 @@
loadQueue.back().instruction()->setSquashed();
loadQueue.back().clear();
- --loads;
-
loadQueue.pop_back();
++stats.squashedLoads;
}
@@ -1282,7 +1276,7 @@
LSQUnit::dumpInsts() const
{
cprintf("Load store queue: Dumping instructions.\n");
- cprintf("Load queue size: %i\n", loads);
+ cprintf("Load queue size: %i\n", loadQueue.size());
cprintf("Load queue: ");
for (const auto& e: loadQueue) {
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 686ca16..19f190b 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -301,7 +301,7 @@
unsigned numFreeStoreEntries();
/** Returns the number of loads in the LQ. */
- int numLoads() { return loads; }
+ int numLoads() { return loadQueue.size(); }
/** Returns the number of stores in the SQ. */
int numStores() { return stores; }
@@ -331,13 +331,13 @@
bool sqFull() { return storeQueue.full(); }
/** Returns if the LQ is empty. */
- bool lqEmpty() const { return loads == 0; }
+ bool lqEmpty() const { return loadQueue.size() == 0; }
/** Returns if the SQ is empty. */
bool sqEmpty() const { return stores == 0; }
/** Returns the number of instructions in the LSQ. */
- unsigned getCount() { return loads + stores; }
+ unsigned getCount() { return loadQueue.size() + stores; }
/** Returns if there are any stores to writeback. */
bool hasStoresToWB() { return storesToWB; }
@@ -495,8 +495,6 @@
/** Should loads be checked for dependency issues */
bool checkLoads;
- /** The number of load instructions in the LQ. */
- int loads;
/** The number of store instructions in the SQ. */
int stores;
/** The number of store instructions in the SQ waiting to writeback. */
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id65776b385f571e4e325b0ffa022bfa765c224bf
Gerrit-Change-Number: 50729
Gerrit-PatchSet: 1
Gerrit-Owner: Tom Rollet <[email protected]>
Gerrit-MessageType: newchange
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