Tom Rollet has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50731 )
Change subject: cpu-o3: remove useless indirection from lsq to cpu
......................................................................
cpu-o3: remove useless indirection from lsq to cpu
Change-Id: Idd2d4277b542da728f0740590ae7ef9ae9b76629
---
M src/cpu/o3/cpu.hh
M src/cpu/o3/lsq.cc
2 files changed, 2 insertions(+), 16 deletions(-)
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 6a02cb8..d7d660a 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -646,20 +646,6 @@
flags, res, std::move(amo_op), byte_enable);
}
- /** CPU read function, forwards read to LSQ. */
- Fault
- read(LSQRequest* req, int load_idx)
- {
- return iew.ldstQueue.read(req, load_idx);
- }
-
- /** CPU write function, forwards write to LSQ. */
- Fault
- write(LSQRequest* req, uint8_t *data, int store_idx)
- {
- return iew.ldstQueue.write(req, data, store_idx);
- }
-
/** Used by the fetch unit to get a hold of the instruction port. */
Port &
getInstPort() override
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index 110c58a..babfa92 100644
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -834,9 +834,9 @@
}
Fault fault;
if (isLoad)
- fault = cpu->read(req, inst->lqIdx);
+ fault = read(req, inst->lqIdx);
else
- fault = cpu->write(req, data, inst->sqIdx);
+ fault = write(req, data, inst->sqIdx);
// inst->getFault() may have the first-fault of a
// multi-access split request at this point.
// Overwrite that only if we got another type of fault
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idd2d4277b542da728f0740590ae7ef9ae9b76629
Gerrit-Change-Number: 50731
Gerrit-PatchSet: 1
Gerrit-Owner: Tom Rollet <tom.rol...@huawei.com>
Gerrit-MessageType: newchange
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