Mahyar Samani has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50752 )
Change subject: tests: Adding tests to evaluate memory modules.
......................................................................
tests: Adding tests to evaluate memory modules.
This change adds a script to validate the statistics reported
by gem5.
Change-Id: Iae0e61c1763c099cf10924a08b3e4989dc31e220
---
A tests/gem5/configs/eval_memory_modules.py
1 file changed, 116 insertions(+), 0 deletions(-)
diff --git a/tests/gem5/configs/eval_memory_modules.py
b/tests/gem5/configs/eval_memory_modules.py
new file mode 100644
index 0000000..a92ac55
--- /dev/null
+++ b/tests/gem5/configs/eval_memory_modules.py
@@ -0,0 +1,116 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This script creates a simple traffic generator. The simulator starts with a
+linear traffic generator, and ends with a random traffic generator. It is
used
+for testing purposes.
+"""
+
+import m5
+import argparse
+
+from m5.objects import Root
+from gem5.components.memory.single_channel import *
+from gem5.components.boards.test_board import TestBoard
+from gem5.components.cachehierarchies.classic.no_cache import NoCache
+from gem5.components.processors.linear_generator import LinearGenerator
+from gem5.components.processors.random_generator import RandomGenerator
+from gem5.components.memory.single_channel import (
+ SingleChannelDDR3_1600,
+ SingleChannelDDR4_2400,
+ SingleChannelHBM,
+)
+
+mem_class_map = {
+ "ddr3": SingleChannelDDR3_1600,
+ "ddr4": SingleChannelDDR4_2400,
+ "hbm": SingleChannelHBM,
+}
+
+generator_class_map = {"linear": LinearGenerator, "random":
RandomGenerator}
+
+parser = argparse.ArgumentParser(
+ description="A traffic generator that can be used to test a gem5 "
+ "memory component."
+)
+
+parser.add_argument(
+ "traffic_mode",
+ type=str,
+ help="Type of traffic to simulate, could be linear or random.",
+)
+
+parser.add_argument(
+ "traffic_rate",
+ type=str,
+ help="Rate at which requests to the memory are created. "
+ "Remember to include the unit. example: 100GB/s",
+)
+
+parser.add_argument(
+ "mem_class", type=str, help="Class of memory to be simulated."
+)
+
+parser.add_argument(
+ "rd_perc",
+ type=int,
+ help="Percentage of read requests among all the created requests.",
+)
+
+args = parser.parse_args()
+
+# This setup does not require a cache heirarchy. We therefore use the
`NoCache`
+# setup.
+cache_hierarchy = NoCache()
+
+memory_class = mem_class_map[args.mem_class]
+memory = memory_class()
+
+generator_class = generator_class_map[args.traffic_mode]
+generator = generator_class(rate=args.traffic_rate)
+
+# We use the Test Board. This is a special board to run traffic generation
+# tasks
+motherboard = TestBoard(
+ clk_freq="4GHz",
+ processor=generator, # We pass the traffic generator as the processor.
+ memory=memory,
+ cache_hierarchy=cache_hierarchy,
+)
+
+motherboard.connect_things()
+
+root = Root(full_system=False, system=motherboard)
+
+m5.instantiate()
+
+generator.start_traffic()
+print("Beginning simulation!")
+exit_event = m5.simulate()
+print(
+ "Exiting @ tick {} because {}.".format(m5.curTick(),
exit_event.getCause())
+)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iae0e61c1763c099cf10924a08b3e4989dc31e220
Gerrit-Change-Number: 50752
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani <[email protected]>
Gerrit-MessageType: newchange
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