Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50389 )
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
Change subject: arch-arm: Remove SPSR write mask
......................................................................
arch-arm: Remove SPSR write mask
We are currently masking out the PAN and UAO field when writing
to the SPSR_ELx register.
This is not needed and we should treat them as RES0 instead if
FEAT_PAN and FEAT_UAO are not implemented
Change-Id: Ib65e3744f365825d2414b8092b3a79324be461b4
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50389
Tested-by: kokoro <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa.cc
1 file changed, 0 insertions(+), 10 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9439d0e..9caf5f7 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2316,16 +2316,6 @@
case MISCREG_AT_S1E3W_Xt:
addressTranslation64(MMU::S1E3Tran, BaseMMU::Write, 0, val);
return;
- case MISCREG_SPSR_EL3:
- case MISCREG_SPSR_EL2:
- case MISCREG_SPSR_EL1:
- {
- RegVal spsr_mask = havePAN ?
- ~(0x2 << 22) : ~(0x3 << 22);
-
- newVal = val & spsr_mask;
- break;
- }
case MISCREG_L2CTLR:
warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
miscRegName[misc_reg], uint32_t(val));
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib65e3744f365825d2414b8092b3a79324be461b4
Gerrit-Change-Number: 50389
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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