Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51014 )
Change subject: arch-arm: Add missing Armv8.1 extensions to the enum
......................................................................
arch-arm: Add missing Armv8.1 extensions to the enum
Change-Id: I90c7eb2b22d317f5a60b020c731948681e9f91a1
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/ArmISA.py
3 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 298d8c3..e98041c 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -47,7 +47,7 @@
class ArmDefaultSERelease(ArmRelease):
extensions = [
- 'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'TME'
+ 'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'FEAT_RDM', 'TME'
]
class ArmISA(BaseISA):
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index f4834d2..c2411a3 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -49,6 +49,9 @@
'FEAT_VHE',
'FEAT_PAN',
'FEAT_LSE',
+ 'FEAT_HPDS',
+ 'FEAT_VMID16',
+ 'FEAT_RDM',
# Armv8.2
'FEAT_SVE',
@@ -97,7 +100,8 @@
class ArmDefaultRelease(Armv8):
extensions = Armv8.extensions + [
- 'FEAT_SVE', 'FEAT_LSE', 'FEAT_PAN', 'FEAT_SEL2'
+ 'FEAT_SVE', 'FEAT_LSE', 'FEAT_PAN',
+ 'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM', 'FEAT_SEL2'
]
class ArmSystem(System):
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 54e574d..a671274 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -352,9 +352,15 @@
miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;
+ /** MISCREG_ID_ISAR5 */
+ // Crypto
miscRegs[MISCREG_ID_ISAR5] = insertBits(
miscRegs[MISCREG_ID_ISAR5], 19, 4,
release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
+ // RDM
+ miscRegs[MISCREG_ID_ISAR5] = insertBits(
+ miscRegs[MISCREG_ID_ISAR5], 27, 24,
+ release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
}
void
@@ -418,6 +424,8 @@
miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
encodePhysAddrRange64(physAddrRange));
+
+ /** MISCREG_ID_AA64ISAR0_EL1 */
// Crypto
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
@@ -426,14 +434,30 @@
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0);
+ // RDM
+ miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+ miscRegs[MISCREG_ID_AA64ISAR0_EL1], 31, 28,
+ release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
+
+ /** MISCREG_ID_AA64MMFR1_EL1 */
+ // VMID16
+ miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
+ miscRegs[MISCREG_ID_AA64MMFR1_EL1], 7, 4,
+ release->has(ArmExtension::FEAT_VMID16) ? 0x2 : 0x0);
// VHE
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0);
+ // HPDS
+ miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
+ miscRegs[MISCREG_ID_AA64MMFR1_EL1], 15, 12,
+ release->has(ArmExtension::FEAT_HPDS) ? 0x1 : 0x0);
// PAN
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0);
+
+
// TME
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 27, 24,
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51014
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I90c7eb2b22d317f5a60b020c731948681e9f91a1
Gerrit-Change-Number: 51014
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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