Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51009 )
Change subject: arch-arm: Prefer haveEL over haveSecurity and
haveVirtualization
......................................................................
arch-arm: Prefer haveEL over haveSecurity and haveVirtualization
The Arm architecture reference manual pseudocode checks for the presence
of an exception level (EL) over "security" and "virtualization"
Change-Id: Ia91a9d1848eddc40776627208386a13afdaafda3
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/mmu.cc
M src/arch/arm/isa/insts/branch.isa
M src/arch/arm/utility.cc
M src/arch/arm/faults.cc
M src/arch/arm/regs/misc.cc
M src/arch/arm/insts/misc64.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
M src/arch/arm/isa/insts/data64.isa
11 files changed, 59 insertions(+), 46 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 1bddd04..c82373a 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -314,8 +314,8 @@
// Check for invalid modes
CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
- assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
- assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
+ assert(ArmSystem::haveEL(tc, EL3) || cpsr.mode != MODE_MON);
+ assert(ArmSystem::haveEL(tc, EL2) || cpsr.mode != MODE_HYP);
switch (cpsr.mode)
{
@@ -330,7 +330,7 @@
if (sctlr.v) {
base = HighVecs;
} else {
- base = ArmSystem::haveSecurity(tc) ?
+ base = ArmSystem::haveEL(tc, EL3) ?
tc->readMiscReg(MISCREG_VBAR) : 0;
}
break;
@@ -345,11 +345,11 @@
Addr vbar;
switch (toEL) {
case EL3:
- assert(ArmSystem::haveSecurity(tc));
+ assert(ArmSystem::haveEL(tc, EL3));
vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
break;
case EL2:
- assert(ArmSystem::haveVirtualization(tc));
+ assert(ArmSystem::haveEL(tc, EL2));
vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
break;
case EL1:
@@ -448,10 +448,10 @@
// Determine target exception level (aarch64) or target execution
// mode (aarch32).
- if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) {
+ if (ArmSystem::haveEL(tc, EL3) && routeToMonitor(tc)) {
toMode = MODE_MON;
toEL = EL3;
- } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) {
+ } else if (ArmSystem::haveEL(tc, EL2) && routeToHyp(tc)) {
toMode = MODE_HYP;
toEL = EL2;
hypRouted = true;
@@ -510,7 +510,7 @@
return;
// ARMv7 (ARM ARM issue C B1.9)
- bool have_security = ArmSystem::haveSecurity(tc);
+ bool have_security = ArmSystem::haveEL(tc, EL3);
FaultBase::invoke(tc);
if (!FullSystem)
@@ -613,7 +613,7 @@
setSyndrome(tc, MISCREG_HSR);
break;
case MODE_HYP:
- assert(ArmSystem::haveVirtualization(tc));
+ assert(ArmSystem::haveEL(tc, EL2));
tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
setSyndrome(tc, MISCREG_HSR);
break;
@@ -648,12 +648,12 @@
spsr_idx = MISCREG_SPSR_EL1;
break;
case EL2:
- assert(ArmSystem::haveVirtualization(tc));
+ assert(ArmSystem::haveEL(tc, EL2));
elr_idx = MISCREG_ELR_EL2;
spsr_idx = MISCREG_SPSR_EL2;
break;
case EL3:
- assert(ArmSystem::haveSecurity(tc));
+ assert(ArmSystem::haveEL(tc, EL3));
elr_idx = MISCREG_ELR_EL3;
spsr_idx = MISCREG_SPSR_EL3;
break;
@@ -766,8 +766,8 @@
// Check for invalid modes
[[maybe_unused]] CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
- assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
- assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
+ assert(ArmSystem::haveEL(tc, EL3) || cpsr.mode != MODE_MON);
+ assert(ArmSystem::haveEL(tc, EL2) || cpsr.mode != MODE_HYP);
// RVBAR is aliased (implemented as) MVBAR in gem5, since the two
// are mutually exclusive; there is no need to check here for
@@ -790,8 +790,8 @@
getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc));
// Unless we have SMC code to get us there, boot in HYP!
- if (ArmSystem::haveVirtualization(tc) &&
- !ArmSystem::haveSecurity(tc)) {
+ if (ArmSystem::haveEL(tc, EL2) &&
+ !ArmSystem::haveEL(tc, EL3)) {
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
cpsr.mode = MODE_HYP;
tc->setMiscReg(MISCREG_CPSR, cpsr);
@@ -1215,7 +1215,7 @@
bool
AbortFault<T>::abortDisable(ThreadContext *tc)
{
- if (ArmSystem::haveSecurity(tc)) {
+ if (ArmSystem::haveEL(tc, EL3)) {
SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
return (!scr.ns || scr.aw);
}
@@ -1472,7 +1472,7 @@
bool
Interrupt::routeToMonitor(ThreadContext *tc) const
{
- assert(ArmSystem::haveSecurity(tc));
+ assert(ArmSystem::haveEL(tc, EL3));
SCR scr = 0;
if (from64)
scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
@@ -1492,7 +1492,7 @@
bool
Interrupt::abortDisable(ThreadContext *tc)
{
- if (ArmSystem::haveSecurity(tc)) {
+ if (ArmSystem::haveEL(tc, EL3)) {
SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
return (!scr.ns || scr.aw);
}
@@ -1505,7 +1505,7 @@
bool
FastInterrupt::routeToMonitor(ThreadContext *tc) const
{
- assert(ArmSystem::haveSecurity(tc));
+ assert(ArmSystem::haveEL(tc, EL3));
SCR scr = 0;
if (from64)
scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
@@ -1525,7 +1525,7 @@
bool
FastInterrupt::abortDisable(ThreadContext *tc)
{
- if (ArmSystem::haveSecurity(tc)) {
+ if (ArmSystem::haveEL(tc, EL3)) {
SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
return (!scr.ns || scr.aw);
}
@@ -1535,9 +1535,9 @@
bool
FastInterrupt::fiqDisable(ThreadContext *tc)
{
- if (ArmSystem::haveVirtualization(tc)) {
+ if (ArmSystem::haveEL(tc, EL2)) {
return true;
- } else if (ArmSystem::haveSecurity(tc)) {
+ } else if (ArmSystem::haveEL(tc, EL3)) {
SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
return (!scr.ns || scr.fw);
}
@@ -1587,7 +1587,7 @@
bool
SystemError::routeToMonitor(ThreadContext *tc) const
{
- assert(ArmSystem::haveSecurity(tc));
+ assert(ArmSystem::haveEL(tc, EL3));
assert(from64);
SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
return scr.ea || fromEL == EL3;
@@ -1659,11 +1659,11 @@
elr_idx = MISCREG_ELR_EL1;
break;
case EL2:
- assert(ArmSystem::haveVirtualization(tc));
+ assert(ArmSystem::haveEL(tc, EL2));
elr_idx = MISCREG_ELR_EL2;
break;
case EL3:
- assert(ArmSystem::haveSecurity(tc));
+ assert(ArmSystem::haveEL(tc, EL3));
elr_idx = MISCREG_ELR_EL3;
break;
default:
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 0c6150a..a0ef0f8 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -99,13 +99,13 @@
}
// Check for traps to hypervisor
- if ((ArmSystem::haveVirtualization(tc) && el <= EL2) &&
+ if ((ArmSystem::haveEL(tc, EL2) && el <= EL2) &&
checkEL2Trap(tc, misc_reg, el, ec, immediate)) {
return std::make_shared<HypervisorTrap>(machInst, immediate, ec);
}
// Check for traps to secure monitor
- if ((ArmSystem::haveSecurity(tc) && el <= EL3) &&
+ if ((ArmSystem::haveEL(tc, EL3) && el <= EL3) &&
checkEL3Trap(tc, misc_reg, el, ec, immediate)) {
return std::make_shared<SecureMonitorTrap>(machInst, immediate,
ec);
}
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index b89acbc..f3d646d 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -700,7 +700,7 @@
}
}
- if (ArmSystem::haveSecurity(tc)) {
+ if (ArmSystem::haveEL(tc, EL3)) {
CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL3);
if (cptr_en_check.tfp) {
return advSIMDFPAccessTrap64(EL3);
@@ -728,8 +728,8 @@
NSACR nsacr, FPEXC fpexc,
bool fpexc_check, bool advsimd)
const
{
- const bool have_virtualization = ArmSystem::haveVirtualization(tc);
- const bool have_security = ArmSystem::haveSecurity(tc);
+ const bool have_virtualization = ArmSystem::haveEL(tc, EL2);
+ const bool have_security = ArmSystem::haveEL(tc, EL3);
const bool is_secure = isSecure(tc);
const ExceptionLevel cur_el = currEL(tc);
@@ -1051,7 +1051,7 @@
}
// Check if access disabled in CPTR_EL3
- if (ArmSystem::haveSecurity(tc)) {
+ if (ArmSystem::haveEL(tc, EL3)) {
CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL3);
if (!cptr_en_check.ez)
return sveAccessTrap(EL3);
diff --git a/src/arch/arm/insts/static_inst.hh
b/src/arch/arm/insts/static_inst.hh
index 383a5b8..95e7f09 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -227,7 +227,7 @@
uint8_t byteMask, bool affectState, bool nmfi, ThreadContext
*tc)
{
bool privileged = (cpsr.mode != MODE_USER);
- bool haveVirt = ArmSystem::haveVirtualization(tc);
+ bool haveVirt = ArmSystem::haveEL(tc, EL2);
bool isSecure = ArmISA::isSecure(tc);
uint32_t bitMask = 0;
diff --git a/src/arch/arm/isa/insts/branch.isa
b/src/arch/arm/isa/insts/branch.isa
index 5acca80..91826a2 100644
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -152,7 +152,7 @@
HSTR hstr = Hstr;
CPSR cpsr = Cpsr;
- if (ArmSystem::haveVirtualization(xc->tcBase()) && hstr.tjdbx &&
+ if (ArmSystem::haveEL(xc->tcBase(), EL2) && hstr.tjdbx &&
!isSecure(xc->tcBase()) && (cpsr.mode != MODE_HYP)) {
fault = std::make_shared<HypervisorTrap>(machInst, op1,
EC_TRAPPED_BXJ);
}
diff --git a/src/arch/arm/isa/insts/data64.isa
b/src/arch/arm/isa/insts/data64.isa
index b302edc..aafab40 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -489,8 +489,8 @@
faultAddr = EA;
HCR hcr = Hcr64;
SCR scr = Scr64;
- if (el == EL1 && ArmSystem::haveVirtualization(xc->tcBase()) &&
- hcr.vm && (scr.ns |
| !ArmSystem::haveSecurity(xc->tcBase()))) {
+ if (el == EL1 && ArmSystem::haveEL(xc->tcBase(), EL2) &&
+ hcr.vm && (scr.ns || !ArmSystem::haveEL(xc->tcBase(),
EL3))) {
memAccessFlags = memAccessFlags | Request::CLEAN;
}
System *sys = xc->tcBase()->getSystemPtr();
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index 2add447..80ba685 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -124,10 +124,10 @@
SCR scr = Scr;
// Filter out the various cases where this instruction isn't defined
- if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
+ if (!FullSystem || !ArmSystem::haveEL(xc->tcBase(), EL2) ||
(cpsr.mode == MODE_USER) ||
(isSecure(xc->tcBase()) && !IsSecureEL2Enabled(xc->tcBase())) ||
- (ArmSystem::haveSecurity(xc->tcBase()) ? !scr.hce : hcr.hcd)) {
+ (ArmSystem::haveEL(xc->tcBase(), EL3) ? !scr.hce : hcr.hcd)) {
fault = disabledFault();
} else {
fault = std::make_shared<HypervisorCall>(machInst, imm);
diff --git a/src/arch/arm/isa/insts/misc64.isa
b/src/arch/arm/isa/insts/misc64.isa
index dc09ade..d516c53 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -99,7 +99,7 @@
SCR scr = Scr64;
CPSR cpsr = Cpsr;
- if (!ArmSystem::haveSecurity(xc->tcBase()) || inUserMode(cpsr) ||
scr.smd) {
+ if (!ArmSystem::haveEL(xc->tcBase(), EL3) || inUserMode(cpsr) ||
scr.smd) {
fault = disabledFault();
} else {
fault = std::make_shared<SecureMonitorCall>(machInst);
diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc
index 96d0bc4..b739457 100644
--- a/src/arch/arm/mmu.cc
+++ b/src/arch/arm/mmu.cc
@@ -542,7 +542,7 @@
MMU::s2PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode,
ThreadContext *tc, CachedState &state, bool r, bool w,
bool x)
{
- assert(ArmSystem::haveVirtualization(tc) && state.aarch64EL != EL2);
+ assert(ArmSystem::haveEL(tc, EL2) && state.aarch64EL != EL2);
// In stage 2 we use the hypervisor access permission bits.
// The following permissions are described in ARM DDI 0487A.f
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 4a94a3e..b1c47ea 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1321,7 +1321,7 @@
{
int reg_as_int = static_cast<int>(reg);
if (miscRegInfo[reg][MISCREG_BANKED]) {
- reg_as_int += (ArmSystem::haveSecurity(tc) &&
+ reg_as_int += (ArmSystem::haveEL(tc, EL3) &&
!ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
}
return reg_as_int;
@@ -1387,7 +1387,7 @@
return false;
}
- bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
+ bool secure = ArmSystem::haveEL(tc, EL3) && !scr.ns;
bool el2_host = EL2Enabled(tc) && hcr.e2h;
switch (currEL(cpsr)) {
@@ -1423,7 +1423,7 @@
return false;
ExceptionLevel el = currEL(cpsr);
- bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
+ bool secure = ArmSystem::haveEL(tc, EL3) && !scr.ns;
bool el2_host = EL2Enabled(tc) && hcr.e2h;
switch (el) {
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 8e99ad6..2baf9c0 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -328,8 +328,8 @@
ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure)
{
// Return true if the specified EL is in aarch32 state.
- const bool have_el3 = ArmSystem::haveSecurity(tc);
- const bool have_el2 = ArmSystem::haveVirtualization(tc);
+ const bool have_el3 = ArmSystem::haveEL(tc, EL3);
+ const bool have_el2 = ArmSystem::haveEL(tc, EL2);
panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't
exist");
panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't
exist");
@@ -1250,8 +1250,8 @@
// NV Extension not implemented yet
bool have_nv_ext = false;
bool unpriv_el1 = currEL(tc) == EL1 &&
- !(ArmSystem::haveVirtualization(tc) &&
- have_nv_ext && hcr.nv == 1 && hcr.nv1 ==
1);
+ !(ArmSystem::haveEL(tc, EL2) &&
+ have_nv_ext && hcr.nv == 1 && hcr.nv1 == 1);
bool unpriv_el2 = ArmSystem::haveEL(tc, EL2) && HaveVirtHostExt(tc) &&
currEL(tc) == EL2 && hcr.e2h == 1 && hcr.tge == 1;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51009
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia91a9d1848eddc40776627208386a13afdaafda3
Gerrit-Change-Number: 51009
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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