Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51012 )
Change subject: arch-arm: Use ArmRelease in the ISA class
......................................................................
arch-arm: Use ArmRelease in the ISA class
This is removing the cached boolean variables from the ISA class.
The ISA is now using a release object.
It is importing it from the ArmSystem in case of a FS simulation,
and it is using its own ArmRelease object in SE mode
This allows us to add/remove SE extensions from python, rather than
hardcoding them in the ISA constructor (in case of SE)
Change-Id: I2b0b2f113e7bb9e28ac86bf2139413e2a71eeb01
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/regs/misc.cc
M src/arch/arm/ArmISA.py
4 files changed, 182 insertions(+), 127 deletions(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 23338d1..0a2bbc6 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -38,13 +38,18 @@
from m5.SimObject import SimObject
from m5.objects.ArmPMU import ArmPMU
-from m5.objects.ArmSystem import SveVectorLength
+from m5.objects.ArmSystem import SveVectorLength, ArmRelease
from m5.objects.BaseISA import BaseISA
from m5.objects.ISACommon import VecRegRenameMode
# Enum for DecoderFlavor
class DecoderFlavor(Enum): vals = ['Generic']
+class ArmDefaultSERelease(ArmRelease):
+ extensions = [
+ 'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'TME', 'FEAT_SEL2'
+ ]
+
class ArmISA(BaseISA):
type = 'ArmISA'
cxx_class = 'gem5::ArmISA::ISA'
@@ -56,6 +61,9 @@
decoderFlavor = Param.DecoderFlavor(
'Generic', "Decoder flavor specification")
+ release_se = Param.ArmRelease(ArmDefaultSERelease(),
+ "Set of features/extensions to use in SE mode")
+
# If no MIDR value is provided, 0x0 is treated by gem5 as follows:
# When 'highest_el_is_64' (AArch64 support) is:
# True -> Cortex-A57 TRM r0p0 MIDR is used
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ee9c556..54e574d 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -103,32 +103,18 @@
// Cache system-level properties
if (FullSystem && system) {
highestELIs64 = system->highestELIs64();
- haveSecurity = system->has(ArmExtension::SECURITY);
- haveLPAE = system->has(ArmExtension::LPAE);
- haveCrypto = system->has(ArmExtension::CRYPTO);
- haveVirtualization = system->has(ArmExtension::VIRTUALIZATION);
haveLargeAsid64 = system->haveLargeAsid64();
physAddrRange = system->physAddrRange();
- haveSVE = system->has(ArmExtension::FEAT_SVE);
- haveVHE = system->has(ArmExtension::FEAT_VHE);
- havePAN = system->has(ArmExtension::FEAT_PAN);
- haveSecEL2 = system->has(ArmExtension::FEAT_SEL2);
sveVL = system->sveVL();
- haveLSE = system->has(ArmExtension::FEAT_LSE);
- haveTME = system->has(ArmExtension::TME);
+
+ release = system->releaseFS();
} else {
highestELIs64 = true; // ArmSystem::highestELIs64 does the same
- haveSecurity = haveLPAE = haveVirtualization = false;
- haveCrypto = true;
haveLargeAsid64 = false;
physAddrRange = 32; // dummy value
- haveSVE = true;
- haveVHE = false;
- havePAN = false;
- haveSecEL2 = true;
sveVL = p.sve_vl_se;
- haveLSE = true;
- haveTME = true;
+
+ release = p.release_se;
}
selfDebug = new SelfDebug();
@@ -264,7 +250,7 @@
miscRegs[MISCREG_FPSID] = p.fpsid;
- if (haveLPAE) {
+ if (release->has(ArmExtension::LPAE)) {
TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
ttbcr.eae = 0;
miscRegs[MISCREG_TTBCR_NS] = ttbcr;
@@ -272,7 +258,7 @@
miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) |
0x5;
}
- if (haveSecurity) {
+ if (release->has(ArmExtension::SECURITY)) {
miscRegs[MISCREG_SCTLR_S] = sctlr;
miscRegs[MISCREG_SCR] = 0;
miscRegs[MISCREG_VBAR_S] = 0;
@@ -319,10 +305,10 @@
// Initialize other control registers
miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
- if (haveSecurity) {
+ if (release->has(ArmExtension::SECURITY)) {
miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
- } else if (haveVirtualization) {
+ } else if (release->has(ArmExtension::VIRTUALIZATION)) {
// also MISCREG_SCTLR_EL2 (by mapping)
miscRegs[MISCREG_HSCTLR] = 0x30c50830;
} else {
@@ -368,7 +354,7 @@
miscRegs[MISCREG_ID_ISAR5] = insertBits(
miscRegs[MISCREG_ID_ISAR5], 19, 4,
- haveCrypto ? 0x1112 : 0x0);
+ release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
}
void
@@ -395,9 +381,9 @@
// SVE
miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0
- if (haveSecurity) {
+ if (release->has(ArmExtension::SECURITY)) {
miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
- } else if (haveVirtualization) {
+ } else if (release->has(ArmExtension::VIRTUALIZATION)) {
miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
} else {
miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
@@ -408,22 +394,22 @@
// EL3
miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
- haveSecurity ? 0x2 : 0x0);
+ release->has(ArmExtension::SECURITY) ? 0x2 : 0x0);
// EL2
miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
- haveVirtualization ? 0x2 : 0x0);
+ release->has(ArmExtension::VIRTUALIZATION) ? 0x2 : 0x0);
// SVE
miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
- haveSVE ? 0x1 : 0x0);
+ release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0);
// SecEL2
miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64PFR0_EL1], 39, 36,
- haveSecEL2 ? 0x1 : 0x0);
+ release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0);
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 39, 36,
- haveSecEL2 ? 0x1 : 0x0);
+ release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0);
// Large ASID support
miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
@@ -435,23 +421,23 @@
// Crypto
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
- haveCrypto ? 0x1112 : 0x0);
+ release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
// LSE
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
- haveLSE ? 0x2 : 0x0);
+ release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0);
// VHE
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
- haveVHE ? 0x1 : 0x0);
+ release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0);
// PAN
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
- havePAN ? 0x1 : 0x0);
+ release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0);
// TME
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 27, 24,
- haveTME ? 0x1 : 0x0);
+ release->has(ArmExtension::TME) ? 0x1 : 0x0);
}
void
@@ -462,7 +448,7 @@
if (tc) {
setupThreadContext();
- if (haveTME) {
+ if (release->has(ArmExtension::TME)) {
std::unique_ptr<BaseHTMCheckpoint> cpt(new HTMCheckpoint());
tc->setHtmCheckpointPtr(std::move(cpt));
}
@@ -596,7 +582,7 @@
switch (unflattenMiscReg(misc_reg)) {
case MISCREG_HCR:
case MISCREG_HCR2:
- if (!haveVirtualization)
+ if (!release->has(ArmExtension::VIRTUALIZATION))
return 0;
break;
case MISCREG_CPACR:
@@ -610,7 +596,7 @@
cpacrMask.asedis = ones;
// Security Extensions may limit the readability of CPACR
- if (haveSecurity) {
+ if (release->has(ArmExtension::SECURITY)) {
scr = readMiscRegNoEffect(MISCREG_SCR);
cpsr = readMiscRegNoEffect(MISCREG_CPSR);
if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
@@ -819,7 +805,8 @@
val &= ~(1 << 14);
// If a CP bit in NSACR is 0 then the corresponding bit in
// HCPTR is RAO/WI
- bool secure_lookup = haveSecurity && isSecure(tc);
+ bool secure_lookup = release->has(ArmExtension::SECURITY) &&
+ isSecure(tc);
if (!secure_lookup) {
RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
val |= (mask ^ 0x7FFF) & 0xBFFF;
@@ -838,19 +825,25 @@
return 0x00000031;
case MISCREG_ID_PFR1:
{ // Timer | Virti | !M Profile | TrustZone | ARMv4
- bool haveTimer = (system->getGenericTimer() != NULL);
- return 0x00000001
- | (haveSecurity ? 0x00000010 : 0x0)
- | (haveVirtualization ? 0x00001000 : 0x0)
- | (haveTimer ? 0x00010000 : 0x0);
+ bool have_timer = (system->getGenericTimer() != nullptr);
+ return 0x00000001 |
+ (release->has(ArmExtension::SECURITY) ?
+ 0x00000010 : 0x0) |
+ (release->has(ArmExtension::VIRTUALIZATION) ?
+ 0x00001000 : 0x0) |
+ (have_timer ? 0x00010000 : 0x0);
}
case MISCREG_ID_AA64PFR0_EL1:
return 0x0000000000000002 | // AArch{64,32} supported at EL0
- 0x0000000000000020 | // EL1
- (haveVirtualization ? 0x0000000000000200 : 0) | // EL2
- (haveSecurity ? 0x0000000000002000 : 0) | // EL3
- (haveSVE ? 0x0000000100000000 : 0) | // SVE
- (haveSecEL2 ? 0x0000001000000000 : 0) | // SecEL2
+ 0x0000000000000020 | // EL1
+ (release->has(ArmExtension::VIRTUALIZATION) ?
+ 0x0000000000000200 : 0) | // EL2
+ (release->has(ArmExtension::SECURITY) ?
+ 0x0000000000002000 : 0) | // EL3
+ (release->has(ArmExtension::FEAT_SVE) ?
+ 0x0000000100000000 : 0) | // SVE
+ (release->has(ArmExtension::FEAT_SEL2) ?
+ 0x0000001000000000 : 0) | // SecEL2
(gicv3CpuInterface ? 0x0000000001000000 : 0);
case MISCREG_ID_AA64PFR1_EL1:
return 0; // bits [63:0] RES0 (reserved for future use)
@@ -975,7 +968,7 @@
cpacrMask.asedis = ones;
// Security Extensions may limit the writability of CPACR
- if (haveSecurity) {
+ if (release->has(ArmExtension::SECURITY)) {
scr = readMiscRegNoEffect(MISCREG_SCR);
CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc,
EL3)) {
@@ -999,7 +992,7 @@
CPACR cpacrMask = 0;
cpacrMask.tta = ones;
cpacrMask.fpen = ones;
- if (haveSVE) {
+ if (release->has(ArmExtension::FEAT_SVE)) {
cpacrMask.zen = ones;
}
newVal &= cpacrMask;
@@ -1015,7 +1008,7 @@
cptrMask.tcpac = ones;
cptrMask.tta = ones;
cptrMask.tfp = ones;
- if (haveSVE) {
+ if (release->has(ArmExtension::FEAT_SVE)) {
cptrMask.tz = ones;
cptrMask.zen = hcr.e2h ? ones : 0;
}
@@ -1024,7 +1017,7 @@
cptrMask = 0;
cptrMask.res1_13_12_el2 = ones;
cptrMask.res1_7_0_el2 = ones;
- if (!haveSVE) {
+ if (!release->has(ArmExtension::FEAT_SVE)) {
cptrMask.res1_8_el2 = ones;
}
cptrMask.res1_9_el2 = ones;
@@ -1040,7 +1033,7 @@
cptrMask.tcpac = ones;
cptrMask.tta = ones;
cptrMask.tfp = ones;
- if (haveSVE) {
+ if (release->has(ArmExtension::FEAT_SVE)) {
cptrMask.ez = ones;
}
newVal &= cptrMask;
@@ -1159,14 +1152,14 @@
}
break;
case MISCREG_HCR2:
- if (!haveVirtualization)
+ if (!release->has(ArmExtension::VIRTUALIZATION))
return;
break;
case MISCREG_HCR:
{
const HDCR mdcr =
tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
selfDebug->setenableTDETGE((HCR)val, mdcr);
- if (!haveVirtualization)
+ if (!release->has(ArmExtension::VIRTUALIZATION))
return;
}
break;
@@ -1440,7 +1433,7 @@
{
// ARM ARM (ARM DDI 0406C.b) B4.1.5
// Valid only with LPAE
- if (!haveLPAE)
+ if (!release->has(ArmExtension::LPAE))
return;
DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
}
@@ -1454,7 +1447,8 @@
scr = readMiscRegNoEffect(MISCREG_SCR);
MiscRegIndex sctlr_idx;
- if (haveSecurity && !highestELIs64 && !scr.ns) {
+ if (release->has(ArmExtension::SECURITY) &&
+ !highestELIs64 && !scr.ns) {
sctlr_idx = MISCREG_SCTLR_S;
} else {
sctlr_idx = MISCREG_SCTLR_NS;
@@ -1462,7 +1456,8 @@
SCTLR sctlr = miscRegs[sctlr_idx];
SCTLR new_sctlr = newVal;
- new_sctlr.nmfi = ((bool)sctlr.nmfi)
&& !haveVirtualization;
+ new_sctlr.nmfi = ((bool)sctlr.nmfi) &&
+ !release->has(ArmExtension::VIRTUALIZATION);
miscRegs[sctlr_idx] = (RegVal)new_sctlr;
getMMUPtr(tc)->invalidateMiscReg();
}
@@ -1508,7 +1503,8 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
- TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIALL tlbiOp(EL1, secure);
tlbiOp(tc);
return;
}
@@ -1518,7 +1514,8 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
- TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIALL tlbiOp(EL1, secure);
tlbiOp.broadcast(tc);
return;
}
@@ -1528,7 +1525,8 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
- ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ ITLBIALL tlbiOp(EL1, secure);
tlbiOp(tc);
return;
}
@@ -1538,7 +1536,8 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
- DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ DTLBIALL tlbiOp(EL1, secure);
tlbiOp(tc);
return;
}
@@ -1552,8 +1551,9 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
TLBIMVA tlbiOp(EL1,
- haveSecurity && !scr.ns,
+ secure,
mbits(newVal, 31, 12),
bits(newVal, 7,0));
@@ -1567,8 +1567,9 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
TLBIMVA tlbiOp(EL1,
- haveSecurity && !scr.ns,
+ secure,
mbits(newVal, 31, 12),
bits(newVal, 7,0));
@@ -1581,8 +1582,9 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
TLBIASID tlbiOp(EL1,
- haveSecurity && !scr.ns,
+ secure,
bits(newVal, 7,0));
tlbiOp(tc);
@@ -1594,8 +1596,9 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
TLBIASID tlbiOp(EL1,
- haveSecurity && !scr.ns,
+ secure,
bits(newVal, 7,0));
tlbiOp.broadcast(tc);
@@ -1611,7 +1614,8 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
- TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIMVAA tlbiOp(EL1, secure,
mbits(newVal, 31,12));
tlbiOp(tc);
@@ -1624,7 +1628,8 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
- TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIMVAA tlbiOp(EL1, secure,
mbits(newVal, 31,12));
tlbiOp.broadcast(tc);
@@ -1640,7 +1645,8 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
- TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIMVAA tlbiOp(EL2, secure,
mbits(newVal, 31,12));
tlbiOp(tc);
@@ -1653,7 +1659,8 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
- TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIMVAA tlbiOp(EL2, secure,
mbits(newVal, 31,12));
tlbiOp.broadcast(tc);
@@ -1669,8 +1676,9 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
TLBIIPA tlbiOp(EL1,
- haveSecurity && !scr.ns,
+ secure,
static_cast<Addr>(bits(newVal, 35, 0)) <<
12);
tlbiOp(tc);
@@ -1684,8 +1692,9 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
TLBIIPA tlbiOp(EL1,
- haveSecurity && !scr.ns,
+ secure,
static_cast<Addr>(bits(newVal, 35, 0)) <<
12);
tlbiOp.broadcast(tc);
@@ -1697,8 +1706,9 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
ITLBIMVA tlbiOp(EL1,
- haveSecurity && !scr.ns,
+ secure,
mbits(newVal, 31, 12),
bits(newVal, 7,0));
@@ -1711,8 +1721,9 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
DTLBIMVA tlbiOp(EL1,
- haveSecurity && !scr.ns,
+ secure,
mbits(newVal, 31, 12),
bits(newVal, 7,0));
@@ -1725,8 +1736,9 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
ITLBIASID tlbiOp(EL1,
- haveSecurity && !scr.ns,
+ secure,
bits(newVal, 7,0));
tlbiOp(tc);
@@ -1738,8 +1750,9 @@
assert32();
scr = readMiscReg(MISCREG_SCR);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
DTLBIASID tlbiOp(EL1,
- haveSecurity && !scr.ns,
+ secure,
bits(newVal, 7,0));
tlbiOp(tc);
@@ -1805,7 +1818,8 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- TLBIALLEL tlbiOp(EL2, haveSecurity && !scr.ns);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIALLEL tlbiOp(EL2, secure);
tlbiOp(tc);
return;
}
@@ -1815,7 +1829,8 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- TLBIALLEL tlbiOp(EL2, haveSecurity && !scr.ns);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIALLEL tlbiOp(EL2, secure);
tlbiOp.broadcast(tc);
return;
}
@@ -1825,7 +1840,8 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- TLBIALLEL tlbiOp(EL1, haveSecurity && !scr.ns);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIALLEL tlbiOp(EL1, secure);
tlbiOp(tc);
return;
}
@@ -1835,7 +1851,8 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- TLBIALLEL tlbiOp(EL1, haveSecurity && !scr.ns);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIALLEL tlbiOp(EL1, secure);
tlbiOp.broadcast(tc);
return;
}
@@ -1844,7 +1861,8 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIVMALL tlbiOp(EL1, secure, true);
tlbiOp(tc);
return;
}
@@ -1855,8 +1873,9 @@
HCR hcr = readMiscReg(MISCREG_HCR_EL2);
bool is_host = (hcr.tge && hcr.e2h);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
ExceptionLevel target_el = is_host ? EL2 : EL1;
- TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns,
false);
+ TLBIVMALL tlbiOp(target_el, secure, false);
tlbiOp(tc);
return;
}
@@ -1865,7 +1884,8 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIVMALL tlbiOp(EL1, secure, true);
tlbiOp.broadcast(tc);
return;
}
@@ -1876,8 +1896,9 @@
HCR hcr = readMiscReg(MISCREG_HCR_EL2);
bool is_host = (hcr.tge && hcr.e2h);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
ExceptionLevel target_el = is_host ? EL2 : EL1;
- TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns,
false);
+ TLBIVMALL tlbiOp(target_el, secure, false);
tlbiOp.broadcast(tc);
return;
}
@@ -1916,7 +1937,8 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIMVA tlbiOp(EL2, secure,
static_cast<Addr>(bits(newVal, 43, 0)) <<
12,
0xbeef);
tlbiOp(tc);
@@ -1929,7 +1951,8 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIMVA tlbiOp(EL2, secure,
static_cast<Addr>(bits(newVal, 43, 0)) <<
12,
0xbeef);
@@ -1947,8 +1970,9 @@
HCR hcr = readMiscReg(MISCREG_HCR_EL2);
bool is_host = (hcr.tge && hcr.e2h);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
ExceptionLevel target_el = is_host ? EL2 : EL1;
- TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
+ TLBIMVA tlbiOp(target_el, secure,
static_cast<Addr>(bits(newVal, 43, 0)) <<
12,
asid);
@@ -1966,8 +1990,9 @@
HCR hcr = readMiscReg(MISCREG_HCR_EL2);
bool is_host = (hcr.tge && hcr.e2h);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
ExceptionLevel target_el = is_host ? EL2 : EL1;
- TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
+ TLBIMVA tlbiOp(target_el, secure,
static_cast<Addr>(bits(newVal, 43, 0)) <<
12,
asid);
@@ -1984,8 +2009,9 @@
HCR hcr = readMiscReg(MISCREG_HCR_EL2);
bool is_host = (hcr.tge && hcr.e2h);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
ExceptionLevel target_el = is_host ? EL2 : EL1;
- TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
+ TLBIASID tlbiOp(target_el, secure, asid);
tlbiOp(tc);
return;
}
@@ -1999,8 +2025,9 @@
HCR hcr = readMiscReg(MISCREG_HCR_EL2);
bool is_host = (hcr.tge && hcr.e2h);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
ExceptionLevel target_el = is_host ? EL2 : EL1;
- TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
+ TLBIASID tlbiOp(target_el, secure, asid);
tlbiOp.broadcast(tc);
return;
}
@@ -2015,8 +2042,9 @@
HCR hcr = readMiscReg(MISCREG_HCR_EL2);
bool is_host = (hcr.tge && hcr.e2h);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
ExceptionLevel target_el = is_host ? EL2 : EL1;
- TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
+ TLBIMVAA tlbiOp(target_el, secure,
static_cast<Addr>(bits(newVal, 43, 0)) << 12);
tlbiOp(tc);
@@ -2031,8 +2059,9 @@
HCR hcr = readMiscReg(MISCREG_HCR_EL2);
bool is_host = (hcr.tge && hcr.e2h);
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
ExceptionLevel target_el = is_host ? EL2 : EL1;
- TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
+ TLBIMVAA tlbiOp(target_el, secure,
static_cast<Addr>(bits(newVal, 43, 0)) << 12);
tlbiOp.broadcast(tc);
@@ -2046,7 +2075,8 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIIPA tlbiOp(EL1, secure,
static_cast<Addr>(bits(newVal, 35, 0)) <<
12);
tlbiOp(tc);
@@ -2060,7 +2090,8 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
+ bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
+ TLBIIPA tlbiOp(EL1, secure,
static_cast<Addr>(bits(newVal, 35, 0)) <<
12);
tlbiOp.broadcast(tc);
@@ -2089,7 +2120,8 @@
{
// If a CP bit in NSACR is 0 then the corresponding bit in
// HCPTR is RAO/WI. Same applies to NSASEDIS
- secure_lookup = haveSecurity && isSecure(tc);
+ secure_lookup = release->has(ArmExtension::SECURITY) &&
+ isSecure(tc);
if (!secure_lookup) {
RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
RegVal mask =
@@ -2119,23 +2151,23 @@
MMU::UserMode, val);
return;
case MISCREG_ATS12NSOPR:
- if (!haveSecurity)
+ if (!release->has(ArmExtension::SECURITY))
panic("Security Extensions required for ATS12NSOPR");
addressTranslation(MMU::S1S2NsTran, BaseMMU::Read, 0, val);
return;
case MISCREG_ATS12NSOPW:
- if (!haveSecurity)
+ if (!release->has(ArmExtension::SECURITY))
panic("Security Extensions required for ATS12NSOPW");
addressTranslation(MMU::S1S2NsTran, BaseMMU::Write, 0, val);
return;
case MISCREG_ATS12NSOUR:
- if (!haveSecurity)
+ if (!release->has(ArmExtension::SECURITY))
panic("Security Extensions required for ATS12NSOUR");
addressTranslation(MMU::S1S2NsTran, BaseMMU::Read,
MMU::UserMode, val);
return;
case MISCREG_ATS12NSOUW:
- if (!haveSecurity)
+ if (!release->has(ArmExtension::SECURITY))
panic("Security Extensions required for ATS12NSOUW");
addressTranslation(MMU::S1S2NsTran, BaseMMU::Write,
MMU::UserMode, val);
@@ -2155,7 +2187,7 @@
// ARM DDI 0406C.b, ARMv7-32
ttbcrMask.n = ones; // T0SZ
- if (haveSecurity) {
+ if (release->has(ArmExtension::SECURITY)) {
ttbcrMask.pd0 = ones;
ttbcrMask.pd1 = ones;
}
@@ -2169,10 +2201,10 @@
ttbcrMask.irgn1 = ones;
ttbcrMask.orgn1 = ones;
ttbcrMask.sh1 = ones;
- if (haveLPAE)
+ if (release->has(ArmExtension::LPAE))
ttbcrMask.eae = ones;
- if (haveLPAE && ttbcrNew.eae) {
+ if (release->has(ArmExtension::LPAE) && ttbcrNew.eae) {
newVal = newVal & ttbcrMask;
} else {
newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
@@ -2185,7 +2217,7 @@
case MISCREG_TTBR1:
{
TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
- if (haveLPAE) {
+ if (release->has(ArmExtension::LPAE)) {
if (ttbcr.eae) {
// ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
// ARMv8 AArch32 bit 63-56 only
@@ -2406,7 +2438,7 @@
if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
- } else if (haveVirtualization && !isSecure(tc) &&
+ } else if (release->has(ArmExtension::VIRTUALIZATION) && !isSecure(tc)
&&
(el == EL0 || el == EL1)) {
len = std::min(
len,
@@ -2416,7 +2448,7 @@
if (el == EL3) {
len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
- } else if (haveSecurity) {
+ } else if (release->has(ArmExtension::SECURITY)) {
len = std::min(
len,
static_cast<unsigned>(
@@ -2521,7 +2553,8 @@
HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
uint8_t max_paddr_bit = 0;
- if (haveLPAE && (ttbcr.eae || tran_type & MMU::HypMode ||
+ if (release->has(ArmExtension::LPAE) &&
+ (ttbcr.eae || tran_type & MMU::HypMode ||
((tran_type & MMU::S1S2NsTran) && hcr.vm) )) {
max_paddr_bit = 39;
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 0e38483..2ef9128 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -88,22 +88,15 @@
// Cached copies of system-level properties
bool highestELIs64;
- bool haveSecurity;
- bool haveLPAE;
- bool haveVirtualization;
- bool haveCrypto;
bool haveLargeAsid64;
uint8_t physAddrRange;
- bool haveSVE;
- bool haveLSE;
- bool haveVHE;
- bool havePAN;
- bool haveSecEL2;
- bool haveTME;
/** SVE vector length in quadwords */
unsigned sveVL;
+ /** This could be either a FS or a SE release */
+ const ArmRelease *release;
+
/**
* If true, accesses to IMPLEMENTATION DEFINED registers are
treated
* as NOP hence not causing UNDEFINED INSTRUCTION.
@@ -735,10 +728,11 @@
}
} else {
if (miscRegInfo[reg][MISCREG_BANKED]) {
- bool secureReg = haveSecurity && !highestELIs64 &&
- inSecureState(miscRegs[MISCREG_SCR],
- miscRegs[MISCREG_CPSR]);
- flat_idx += secureReg ? 2 : 1;
+ bool secure_reg = release->has(ArmExtension::SECURITY)
&&
+ !highestELIs64 &&
+ inSecureState(miscRegs[MISCREG_SCR],
+
miscRegs[MISCREG_CPSR]);
+ flat_idx += secure_reg ? 2 : 1;
} else {
flat_idx = snsBankedIndex64((MiscRegIndex)reg,
!inSecureState(miscRegs[MISCREG_SCR],
@@ -759,7 +753,7 @@
if (hcr.e2h == 0x0 || currEL(tc) != EL2)
return misc_reg;
SCR scr = readMiscRegNoEffect(MISCREG_SCR_EL3);
- bool sec_el2 = scr.eel2 && haveSecEL2;
+ bool sec_el2 = scr.eel2 &&
release->has(ArmExtension::FEAT_SEL2);
switch(misc_reg) {
case MISCREG_SPSR_EL1:
return MISCREG_SPSR_EL2;
@@ -825,7 +819,8 @@
{
int reg_as_int = static_cast<int>(reg);
if (miscRegInfo[reg][MISCREG_BANKED64]) {
- reg_as_int += (haveSecurity && !ns) ? 2 : 1;
+ reg_as_int += (release->has(ArmExtension::SECURITY)
&& !ns) ?
+ 2 : 1;
}
return reg_as_int;
}
@@ -840,7 +835,7 @@
}
// do additional S/NS flattenings if mapped to NS while in S
- bool S = haveSecurity && !highestELIs64 &&
+ bool S = release->has(ArmExtension::SECURITY)
&& !highestELIs64 &&
inSecureState(miscRegs[MISCREG_SCR],
miscRegs[MISCREG_CPSR]);
int lower = lookUpMiscReg[flat_idx].lower;
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index b1c47ea..d586e0f 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3410,7 +3410,7 @@
// This boolean variable specifies if the system is running in aarch32
at
// EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or
it
// is running in aarch64 (aarch32EL3 = false)
- bool aarch32EL3 = haveSecurity && !highestELIs64;
+ bool aarch32EL3 = release->has(ArmExtension::SECURITY)
&& !highestELIs64;
// Set Privileged Access Never on taking an exception to EL1 (Arm
8.1+),
// unsupported
@@ -4946,7 +4946,7 @@
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_PAN)
.allPrivileges().exceptUserMode()
- .implemented(havePAN);
+ .implemented(release->has(ArmExtension::FEAT_PAN));
InitReg(MISCREG_UAO)
.allPrivileges().exceptUserMode();
InitReg(MISCREG_NZCV)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51012
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2b0b2f113e7bb9e28ac86bf2139413e2a71eeb01
Gerrit-Change-Number: 51012
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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