[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add missing Armv8.2 extensions to the enum

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51017 )

Change subject: arch-arm: Add missing Armv8.2 extensions to the enum
......................................................................

arch-arm: Add missing Armv8.2 extensions to the enum

Change-Id: Ie98d06909fada7ca1370f2283ef0fce61b6dc953
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/system.cc
3 files changed, 32 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index fbb2cff..4ec0838 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -55,6 +55,9 @@

         # Armv8.2
         'FEAT_SVE',
+        'FEAT_UAO',
+        'FEAT_LVA', # Optional in Armv8.2
+        'FEAT_LPA', # Optional in Armv8.2

         # Armv8.4
         'FEAT_SEL2',
@@ -100,8 +103,12 @@

 class ArmDefaultRelease(Armv8):
     extensions = Armv8.extensions + [
-        'FEAT_SVE', 'FEAT_LSE', 'FEAT_PAN',
-        'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM', 'FEAT_SEL2'
+        # Armv8.1
+        'FEAT_LSE', 'FEAT_PAN', 'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM',
+        # Armv8.2
+        'FEAT_UAO', 'FEAT_LVA', 'FEAT_LPA', 'FEAT_SVE',
+        # Armv8.4
+        'FEAT_SEL2'
     ]

 class Armv81(Armv8):
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 84d9e51..6691901 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -455,6 +455,16 @@
         miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
         release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0);

+    /** MISCREG_ID_AA64MMFR2_EL1 */
+    // UAO
+    miscRegs[MISCREG_ID_AA64MMFR2_EL1] = insertBits(
+        miscRegs[MISCREG_ID_AA64MMFR2_EL1], 7, 4,
+        release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0);
+    // LVA
+    miscRegs[MISCREG_ID_AA64MMFR2_EL1] = insertBits(
+        miscRegs[MISCREG_ID_AA64MMFR2_EL1], 19, 16,
+        release->has(ArmExtension::FEAT_LVA) ? 0x1 : 0x0);
+

     // TME
     miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 4edc350..747695f 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -102,7 +102,9 @@
     if (_highestELIs64 && (
             _physAddrRange64 < 32 ||
             _physAddrRange64 > MaxPhysAddrRange ||
-            (_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) {
+            (_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42) ||
+            (_physAddrRange64 == 52  
&& !release->has(ArmExtension::FEAT_LPA))))
+    {
         fatal("Invalid physical address range (%d)\n", _physAddrRange64);
     }
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie98d06909fada7ca1370f2283ef0fce61b6dc953
Gerrit-Change-Number: 51017
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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