Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51237 )
Change subject: arch: Make the (read|set)MiscReg methods virtual.
......................................................................
arch: Make the (read|set)MiscReg methods virtual.
They will then be accessible through the base class. This adds some
small hypothetical amount of overhead to each call, but a quick test
booting linux on x86 does not show any significant slowdown.
Change-Id: If706ddf173d4e24d85468fb118b45099acf3c05b
---
M src/arch/generic/isa.hh
M src/arch/riscv/decoder.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/sparc/decoder.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/power/isa.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/mips/decoder.hh
M src/arch/x86/isa.cc
M src/arch/x86/isa.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/power/decoder.hh
M src/arch/x86/decoder.hh
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
19 files changed, 260 insertions(+), 227 deletions(-)
diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 1867e90..4e90efb 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -42,6 +42,7 @@
#include "arch/arm/isa.hh"
#include "arch/arm/utility.hh"
+#include "base/cast.hh"
#include "base/trace.hh"
#include "debug/Decoder.hh"
#include "sim/full_system.hh"
@@ -54,14 +55,14 @@
GenericISA::BasicDecodeCache<Decoder, ExtMachInst> Decoder::defaultCache;
-Decoder::Decoder(ISA* isa)
+Decoder::Decoder(BaseISA* isa)
: InstDecoder(&data), data(0), fpscrLen(0), fpscrStride(0),
- decoderFlavor(isa->decoderFlavor())
+ decoderFlavor(safe_cast<ISA *>(isa)->decoderFlavor())
{
reset();
// Initialize SVE vector length
- sveLen = (isa->getCurSveVecLenInBitsAtReset() >> 7) - 1;
+ sveLen = (safe_cast<ISA *>(isa)->getCurSveVecLenInBitsAtReset() >> 7)
- 1;
}
void
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 34abf5e..b9f240b 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -55,10 +55,11 @@
namespace gem5
{
+class BaseISA;
+
namespace ArmISA
{
-class ISA;
class Decoder : public InstDecoder
{
protected:
@@ -132,7 +133,7 @@
}
public: // Decoder API
- Decoder(ISA* isa = nullptr);
+ Decoder(BaseISA* isa = nullptr);
/** Reset the decoders internal state. */
void reset();
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 681bc53..076b551 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -579,12 +579,12 @@
}
RegVal
-ISA::readMiscRegNoEffect(int misc_reg) const
+ISA::readMiscRegNoEffect(RegIndex idx) const
{
- assert(misc_reg < NUM_MISCREGS);
+ assert(idx < NUM_MISCREGS);
- const auto ® = lookUpMiscReg[misc_reg]; // bit masks
- const auto &map = getMiscIndices(misc_reg);
+ const auto ® = lookUpMiscReg[idx]; // bit masks
+ const auto &map = getMiscIndices(idx);
int lower = map.first, upper = map.second;
// NB!: apply architectural masks according to desired register,
// despite possibly getting value from different (mapped) register.
@@ -592,25 +592,25 @@
|(miscRegs[upper] << 32));
if (val & reg.res0()) {
DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
- miscRegName[misc_reg], val & reg.res0());
+ miscRegName[idx], val & reg.res0());
}
if ((val & reg.res1()) != reg.res1()) {
DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
- miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
+ miscRegName[idx], (val & reg.res1()) ^ reg.res1());
}
return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
}
RegVal
-ISA::readMiscReg(int misc_reg)
+ISA::readMiscReg(RegIndex idx)
{
CPSR cpsr = 0;
PCState pc = 0;
SCR scr = 0;
- if (misc_reg == MISCREG_CPSR) {
- cpsr = miscRegs[misc_reg];
+ if (idx == MISCREG_CPSR) {
+ cpsr = miscRegs[idx];
pc = tc->pcState();
cpsr.j = pc.jazelle() ? 1 : 0;
cpsr.t = pc.thumb() ? 1 : 0;
@@ -618,18 +618,18 @@
}
#ifndef NDEBUG
- if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
- if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
+ if (!miscRegInfo[idx][MISCREG_IMPLEMENTED]) {
+ if (miscRegInfo[idx][MISCREG_WARN_NOT_FAIL])
warn("Unimplemented system register %s read.\n",
- miscRegName[misc_reg]);
+ miscRegName[idx]);
else
panic("Unimplemented system register %s read.\n",
- miscRegName[misc_reg]);
+ miscRegName[idx]);
}
#endif
- misc_reg = redirectRegVHE(tc, misc_reg);
+ idx = redirectRegVHE(tc, idx);
- switch (unflattenMiscReg(misc_reg)) {
+ switch (unflattenMiscReg(idx)) {
case MISCREG_HCR:
case MISCREG_HCR2:
if (!release->has(ArmExtension::VIRTUALIZATION))
@@ -659,7 +659,7 @@
RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
val &= cpacrMask;
DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
- miscRegName[misc_reg], val);
+ miscRegName[idx], val);
return val;
}
case MISCREG_MPIDR:
@@ -668,14 +668,14 @@
case MISCREG_VMPIDR:
case MISCREG_VMPIDR_EL2:
// top bit defined as RES1
- return readMiscRegNoEffect(misc_reg) | 0x80000000;
+ return readMiscRegNoEffect(idx) | 0x80000000;
case MISCREG_ID_AFR0: // not implemented, so alias MIDR
case MISCREG_REVIDR: // not implemented, so alias MIDR
case MISCREG_MIDR:
cpsr = readMiscRegNoEffect(MISCREG_CPSR);
scr = readMiscRegNoEffect(MISCREG_SCR);
if ((cpsr.mode == MODE_HYP) || isSecure(tc)) {
- return readMiscRegNoEffect(misc_reg);
+ return readMiscRegNoEffect(idx);
} else {
return readMiscRegNoEffect(MISCREG_VPIDR);
}
@@ -733,7 +733,7 @@
case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
case MISCREG_PMCR ... MISCREG_PMOVSSET:
- return pmu->readMiscReg(misc_reg);
+ return pmu->readMiscReg(idx);
case MISCREG_CPSR_Q:
panic("shouldn't be reading this register seperately\n");
@@ -850,7 +850,7 @@
return 0x04; // DC ZVA clear 64-byte chunks
case MISCREG_HCPTR:
{
- RegVal val = readMiscRegNoEffect(misc_reg);
+ RegVal val = readMiscRegNoEffect(idx);
// The trap bit associated with CP14 is defined as RAZ
val &= ~(1 << 14);
// If a CP bit in NSACR is 0 then the corresponding bit in
@@ -901,27 +901,27 @@
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
- return getGenericTimer().readMiscReg(misc_reg);
+ return getGenericTimer().readMiscReg(idx);
case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
- return getGICv3CPUInterface().readMiscReg(misc_reg);
+ return getGICv3CPUInterface().readMiscReg(idx);
default:
break;
}
- return readMiscRegNoEffect(misc_reg);
+ return readMiscRegNoEffect(idx);
}
void
-ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
+ISA::setMiscRegNoEffect(RegIndex idx, RegVal val)
{
- assert(misc_reg < NUM_MISCREGS);
+ assert(idx < NUM_MISCREGS);
- const auto ® = lookUpMiscReg[misc_reg]; // bit masks
- const auto &map = getMiscIndices(misc_reg);
+ const auto ® = lookUpMiscReg[idx]; // bit masks
+ const auto &map = getMiscIndices(idx);
int lower = map.first, upper = map.second;
auto v = (val & ~reg.wi()) | reg.rao();
@@ -929,23 +929,23 @@
miscRegs[lower] = bits(v, 31, 0);
miscRegs[upper] = bits(v, 63, 32);
DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
- miscRegName[misc_reg], misc_reg, lower, upper, v);
+ miscRegName[idx], idx, lower, upper, v);
} else {
miscRegs[lower] = v;
DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
- miscRegName[misc_reg], misc_reg, lower, v);
+ miscRegName[idx], idx, lower, v);
}
}
void
-ISA::setMiscReg(int misc_reg, RegVal val)
+ISA::setMiscReg(RegIndex idx, RegVal val)
{
RegVal newVal = val;
bool secure_lookup;
SCR scr;
- if (misc_reg == MISCREG_CPSR) {
+ if (idx == MISCREG_CPSR) {
updateRegMap(val);
@@ -957,7 +957,7 @@
}
DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d
mode:%#x\n",
- miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a,
cpsr.mode);
+ miscRegs[idx], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
PCState pc = tc->pcState();
pc.nextThumb(cpsr.t);
pc.nextJazelle(cpsr.j);
@@ -975,7 +975,7 @@
tc->pcState(pc);
}
- setMiscRegNoEffect(misc_reg, newVal);
+ setMiscRegNoEffect(idx, newVal);
if (old_mode != cpsr.mode) {
getMMUPtr(tc)->invalidateMiscReg();
@@ -994,18 +994,18 @@
}
} else {
#ifndef NDEBUG
- if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
- if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
+ if (!miscRegInfo[idx][MISCREG_IMPLEMENTED]) {
+ if (miscRegInfo[idx][MISCREG_WARN_NOT_FAIL])
warn("Unimplemented system register %s write with %#x.\n",
- miscRegName[misc_reg], val);
+ miscRegName[idx], val);
else
panic("Unimplemented system register %s write with %#x.\n",
- miscRegName[misc_reg], val);
+ miscRegName[idx], val);
}
#endif
- misc_reg = redirectRegVHE(tc, misc_reg);
+ idx = redirectRegVHE(tc, idx);
- switch (unflattenMiscReg(misc_reg)) {
+ switch (unflattenMiscReg(idx)) {
case MISCREG_CPACR:
{
@@ -1033,7 +1033,7 @@
newVal &= cpacrMask;
newVal |= old_val & ~cpacrMask;
DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
- miscRegName[misc_reg], newVal);
+ miscRegName[idx], newVal);
}
break;
case MISCREG_CPACR_EL1:
@@ -1047,7 +1047,7 @@
}
newVal &= cpacrMask;
DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
- miscRegName[misc_reg], newVal);
+ miscRegName[idx], newVal);
}
break;
case MISCREG_CPTR_EL2:
@@ -1073,7 +1073,7 @@
cptrMask.res1_9_el2 = ones;
newVal |= cptrMask;
DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
- miscRegName[misc_reg], newVal);
+ miscRegName[idx], newVal);
}
break;
case MISCREG_CPTR_EL3:
@@ -1088,7 +1088,7 @@
}
newVal &= cptrMask;
DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
- miscRegName[misc_reg], newVal);
+ miscRegName[idx], newVal);
}
break;
case MISCREG_CSSELR:
@@ -1151,7 +1151,7 @@
newVal = (newVal & (uint32_t)fpscrMask) |
(readMiscRegNoEffect(MISCREG_FPSCR) &
~(uint32_t)fpscrMask);
- misc_reg = MISCREG_FPSCR;
+ idx = MISCREG_FPSCR;
}
break;
case MISCREG_FPCR:
@@ -1168,28 +1168,28 @@
newVal = (newVal & (uint32_t)fpscrMask) |
(readMiscRegNoEffect(MISCREG_FPSCR) &
~(uint32_t)fpscrMask);
- misc_reg = MISCREG_FPSCR;
+ idx = MISCREG_FPSCR;
}
break;
case MISCREG_CPSR_Q:
{
assert(!(newVal & ~CpsrMaskQ));
newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
- misc_reg = MISCREG_CPSR;
+ idx = MISCREG_CPSR;
}
break;
case MISCREG_FPSCR_QC:
{
newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
(newVal & FpscrQcMask);
- misc_reg = MISCREG_FPSCR;
+ idx = MISCREG_FPSCR;
}
break;
case MISCREG_FPSCR_EXC:
{
newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
(newVal & FpscrExcMask);
- misc_reg = MISCREG_FPSCR;
+ idx = MISCREG_FPSCR;
}
break;
case MISCREG_FPEXC:
@@ -2155,7 +2155,7 @@
case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
case MISCREG_PMCR ... MISCREG_PMOVSSET:
- pmu->setMiscReg(misc_reg, newVal);
+ pmu->setMiscReg(idx, newVal);
break;
@@ -2181,10 +2181,10 @@
break;
}
case MISCREG_HDFAR: // alias for secure DFAR
- misc_reg = MISCREG_DFAR_S;
+ idx = MISCREG_DFAR_S;
break;
case MISCREG_HIFAR: // alias for secure IFAR
- misc_reg = MISCREG_IFAR_S;
+ idx = MISCREG_IFAR_S;
break;
case MISCREG_ATS1CPR:
addressTranslation(MMU::S1CTran, BaseMMU::Read, 0, val);
@@ -2323,7 +2323,7 @@
CPSR cpsr = miscRegs[MISCREG_CPSR];
cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
newVal = cpsr;
- misc_reg = MISCREG_CPSR;
+ idx = MISCREG_CPSR;
}
break;
case MISCREG_SP_EL0:
@@ -2340,7 +2340,7 @@
CPSR cpsr = miscRegs[MISCREG_CPSR];
cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
newVal = cpsr;
- misc_reg = MISCREG_CPSR;
+ idx = MISCREG_CPSR;
}
break;
case MISCREG_CURRENTEL:
@@ -2348,7 +2348,7 @@
CPSR cpsr = miscRegs[MISCREG_CPSR];
cpsr.el = (uint8_t) ((CPSR) newVal).el;
newVal = cpsr;
- misc_reg = MISCREG_CPSR;
+ idx = MISCREG_CPSR;
}
break;
case MISCREG_PAN:
@@ -2359,7 +2359,7 @@
CPSR cpsr = miscRegs[MISCREG_CPSR];
cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
newVal = cpsr;
- misc_reg = MISCREG_CPSR;
+ idx = MISCREG_CPSR;
}
break;
case MISCREG_UAO:
@@ -2370,7 +2370,7 @@
CPSR cpsr = miscRegs[MISCREG_CPSR];
cpsr.uao = (uint8_t) ((CPSR) newVal).uao;
newVal = cpsr;
- misc_reg = MISCREG_CPSR;
+ idx = MISCREG_CPSR;
}
break;
case MISCREG_AT_S1E1R_Xt:
@@ -2415,18 +2415,18 @@
return;
case MISCREG_L2CTLR:
warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
- miscRegName[misc_reg], uint32_t(val));
+ miscRegName[idx], uint32_t(val));
break;
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
- getGenericTimer().setMiscReg(misc_reg, newVal);
+ getGenericTimer().setMiscReg(idx, newVal);
break;
case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
- getGICv3CPUInterface().setMiscReg(misc_reg, newVal);
+ getGICv3CPUInterface().setMiscReg(idx, newVal);
return;
case MISCREG_ZCR_EL3:
case MISCREG_ZCR_EL2:
@@ -2434,7 +2434,7 @@
tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7)
- 1);
break;
}
- setMiscRegNoEffect(misc_reg, newVal);
+ setMiscRegNoEffect(idx, newVal);
}
}
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 8c30e8b..a3331cf 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -529,10 +529,10 @@
return arm_isa->getSelfDebug();
}
- RegVal readMiscRegNoEffect(int misc_reg) const;
- RegVal readMiscReg(int misc_reg);
- void setMiscRegNoEffect(int misc_reg, RegVal val);
- void setMiscReg(int misc_reg, RegVal val);
+ RegVal readMiscRegNoEffect(RegIndex idx) const override;
+ RegVal readMiscReg(RegIndex idx) override;
+ void setMiscRegNoEffect(RegIndex idx, RegVal val) override;
+ void setMiscReg(RegIndex, RegVal val) override;
int
flattenMiscIndex(int reg) const
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 95bfb5b..f9f07ba 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -68,6 +68,12 @@
public:
virtual void clear() {}
+ virtual RegVal readMiscRegNoEffect(RegIndex idx) const = 0;
+ virtual RegVal readMiscReg(RegIndex idx) = 0;
+
+ virtual void setMiscRegNoEffect(RegIndex idx, RegVal val) = 0;
+ virtual void setMiscReg(RegIndex idx, RegVal val) = 0;
+
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext
*old_tc) {}
virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
diff --git a/src/arch/mips/decoder.hh b/src/arch/mips/decoder.hh
index 0e8e2ca..4671d34 100644
--- a/src/arch/mips/decoder.hh
+++ b/src/arch/mips/decoder.hh
@@ -40,10 +40,11 @@
namespace gem5
{
+class BaseISA;
+
namespace MipsISA
{
-class ISA;
class Decoder : public InstDecoder
{
protected:
@@ -53,7 +54,7 @@
bool instDone;
public:
- Decoder(ISA* isa = nullptr) : InstDecoder(&machInst), instDone(false)
+ Decoder(BaseISA* isa=nullptr) : InstDecoder(&machInst), instDone(false)
{}
void
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 86f19c0..92567f7 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -457,54 +457,52 @@
}
RegVal
-ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
+ISA::readMiscRegNoEffect(RegIndex idx, ThreadID tid) const
{
- unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
+ unsigned reg_sel = (bankType[idx] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
- misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
- miscRegFile[misc_reg][reg_sel]);
- return miscRegFile[misc_reg][reg_sel];
+ idx / 8, idx % 8, miscRegNames[idx],
miscRegFile[idx][reg_sel]);
+ return miscRegFile[idx][reg_sel];
}
//@TODO: MIPS MT's register view automatically connects
// Status to TCStatus depending on current thread
//template <class TC>
RegVal
-ISA::readMiscReg(int misc_reg, ThreadID tid)
+ISA::readMiscReg(RegIndex idx, ThreadID tid)
{
- unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
+ unsigned reg_sel = (bankType[idx] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA,
"Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
- misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
- miscRegFile[misc_reg][reg_sel]);
+ idx / 8, idx % 8, miscRegNames[idx],
miscRegFile[idx][reg_sel]);
- return miscRegFile[misc_reg][reg_sel];
+ return miscRegFile[idx][reg_sel];
}
void
-ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
+ISA::setMiscRegNoEffect(RegIndex idx, RegVal val, ThreadID tid)
{
- unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
+ unsigned reg_sel = (bankType[idx] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA,
"[tid:%i] Setting (direct set) CP0 Register:%u "
"Select:%u (%s) to %#x.\n",
- tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
+ tid, idx / 8, idx % 8, miscRegNames[idx], val);
- miscRegFile[misc_reg][reg_sel] = val;
+ miscRegFile[idx][reg_sel] = val;
}
void
-ISA::setRegMask(int misc_reg, RegVal val, ThreadID tid)
+ISA::setRegMask(RegIndex idx, RegVal val, ThreadID tid)
{
- unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
+ unsigned reg_sel = (bankType[idx] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA,
"[tid:%i] Setting CP0 Register: %u Select: %u (%s) to %#x\n",
- tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
- miscRegFile_WriteMask[misc_reg][reg_sel] = val;
+ tid, idx / 8, idx % 8, miscRegNames[idx], val);
+ miscRegFile_WriteMask[idx][reg_sel] = val;
}
// PROGRAMMER'S NOTES:
@@ -512,19 +510,19 @@
// be overwritten. Make sure to handle those particular registers
// with care!
void
-ISA::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
+ISA::setMiscReg(RegIndex idx, RegVal val, ThreadID tid)
{
- int reg_sel = (bankType[misc_reg] == perThreadContext)
+ int reg_sel = (bankType[idx] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA,
"[tid:%i] Setting CP0 Register:%u "
"Select:%u (%s) to %#x, with effect.\n",
- tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
+ tid, idx / 8, idx % 8, miscRegNames[idx], val);
- RegVal cp0_val = filterCP0Write(misc_reg, reg_sel, val);
+ RegVal cp0_val = filterCP0Write(idx, reg_sel, val);
- miscRegFile[misc_reg][reg_sel] = cp0_val;
+ miscRegFile[idx][reg_sel] = cp0_val;
scheduleCP0Update(tc->getCpuPtr(), Cycles(1));
}
@@ -535,22 +533,22 @@
* (setRegWithEffect)
*/
RegVal
-ISA::filterCP0Write(int misc_reg, int reg_sel, RegVal val)
+ISA::filterCP0Write(RegIndex idx, int reg_sel, RegVal val)
{
RegVal retVal = val;
// Mask off read-only regions
- retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
- RegVal curVal = miscRegFile[misc_reg][reg_sel];
+ retVal &= miscRegFile_WriteMask[idx][reg_sel];
+ RegVal curVal = miscRegFile[idx][reg_sel];
// Mask off current alue with inverse mask (clear writeable bits)
- curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
+ curVal &= (~miscRegFile_WriteMask[idx][reg_sel]);
retVal |= curVal; // Combine the two
DPRINTF(MipsPRA,
"filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
"current val: %lx, written val: %x\n",
- miscRegFile_WriteMask[misc_reg][reg_sel],
- ~miscRegFile_WriteMask[misc_reg][reg_sel],
- val, miscRegFile[misc_reg][reg_sel], retVal);
+ miscRegFile_WriteMask[idx][reg_sel],
+ ~miscRegFile_WriteMask[idx][reg_sel],
+ val, miscRegFile[idx][reg_sel], retVal);
return retVal;
}
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 4f937e3..ba50b7a 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -91,18 +91,37 @@
//////////////////////////////////////////////////////////
//@TODO: MIPS MT's register view automatically connects
// Status to TCStatus depending on current thread
- void updateCP0ReadView(int misc_reg, ThreadID tid) { }
- RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
+ void updateCP0ReadView(RegIndex idx, ThreadID tid) { }
+ RegVal readMiscRegNoEffect(RegIndex idx, ThreadID tid) const;
+ RegVal
+ readMiscRegNoEffect(RegIndex idx) const override
+ {
+ return readMiscRegNoEffect(idx, 0);
+ }
- //template <class TC>
- RegVal readMiscReg(int misc_reg, ThreadID tid = 0);
+ RegVal readMiscReg(RegIndex idx, ThreadID tid);
+ RegVal
+ readMiscReg(RegIndex idx) override
+ {
+ return readMiscReg(idx, 0);
+ }
- RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val);
- void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0);
- void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
+ RegVal filterCP0Write(RegIndex idx, int reg_sel, RegVal val);
+ void setRegMask(RegIndex idx, RegVal val, ThreadID tid = 0);
- //template <class TC>
- void setMiscReg(int misc_reg, RegVal val, ThreadID tid=0);
+ void setMiscRegNoEffect(RegIndex idx, RegVal val, ThreadID tid);
+ void
+ setMiscRegNoEffect(RegIndex idx, RegVal val) override
+ {
+ setMiscRegNoEffect(idx, val, 0);
+ }
+
+ void setMiscReg(RegIndex idx, RegVal val, ThreadID tid);
+ void
+ setMiscReg(RegIndex idx, RegVal val) override
+ {
+ setMiscReg(idx, val, 0);
+ }
//////////////////////////////////////////////////////////
//
diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh
index c30af91..4aa1d58 100644
--- a/src/arch/power/decoder.hh
+++ b/src/arch/power/decoder.hh
@@ -39,10 +39,11 @@
namespace gem5
{
+class BaseISA;
+
namespace PowerISA
{
-class ISA;
class Decoder : public InstDecoder
{
protected:
@@ -51,7 +52,7 @@
bool instDone;
public:
- Decoder(ISA* isa=nullptr) : InstDecoder(&emi), instDone(false) {}
+ Decoder(BaseISA* isa=nullptr) : InstDecoder(&emi), instDone(false) {}
void
process()
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 8fe50b5..d6a4f95 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -52,32 +52,29 @@
class ISA : public BaseISA
{
protected:
- RegVal dummy;
RegVal miscRegs[NUM_MISCREGS];
public:
RegVal
- readMiscRegNoEffect(int misc_reg) const
+ readMiscRegNoEffect(RegIndex idx) const override
{
fatal("Power does not currently have any misc regs defined\n");
- return dummy;
}
RegVal
- readMiscReg(int misc_reg)
- {
- fatal("Power does not currently have any misc regs defined\n");
- return dummy;
- }
-
- void
- setMiscRegNoEffect(int misc_reg, RegVal val)
+ readMiscReg(RegIndex idx) override
{
fatal("Power does not currently have any misc regs defined\n");
}
void
- setMiscReg(int misc_reg, RegVal val)
+ setMiscRegNoEffect(RegIndex idx, RegVal val) override
+ {
+ fatal("Power does not currently have any misc regs defined\n");
+ }
+
+ void
+ setMiscReg(RegIndex idx, RegVal val) override
{
fatal("Power does not currently have any misc regs defined\n");
}
diff --git a/src/arch/riscv/decoder.hh b/src/arch/riscv/decoder.hh
index 8f5083b..cb790dc 100644
--- a/src/arch/riscv/decoder.hh
+++ b/src/arch/riscv/decoder.hh
@@ -41,10 +41,11 @@
namespace gem5
{
+class BaseISA;
+
namespace RiscvISA
{
-class ISA;
class Decoder : public InstDecoder
{
private:
@@ -67,7 +68,7 @@
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
public:
- Decoder(ISA* isa=nullptr) : InstDecoder(&machInst) { reset(); }
+ Decoder(BaseISA* isa=nullptr) : InstDecoder(&machInst) { reset(); }
void process() {}
void reset();
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 83c2abc..18a6493 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -270,22 +270,19 @@
}
RegVal
-ISA::readMiscRegNoEffect(int misc_reg) const
+ISA::readMiscRegNoEffect(RegIndex idx) const
{
- if (misc_reg > NUM_MISCREGS || misc_reg < 0) {
- // Illegal CSR
- panic("Illegal CSR index %#x\n", misc_reg);
- return -1;
- }
+ // Illegal CSR
+ panic_if(idx > NUM_MISCREGS, "Illegal CSR index %#x\n", idx);
DPRINTF(RiscvMisc, "Reading MiscReg %s (%d): %#x.\n",
- MiscRegNames[misc_reg], misc_reg, miscRegFile[misc_reg]);
- return miscRegFile[misc_reg];
+ MiscRegNames[idx], idx, miscRegFile[idx]);
+ return miscRegFile[idx];
}
RegVal
-ISA::readMiscReg(int misc_reg)
+ISA::readMiscReg(RegIndex idx)
{
- switch (misc_reg) {
+ switch (idx) {
case MISCREG_HARTID:
return tc->contextId();
case MISCREG_CYCLE:
@@ -331,7 +328,7 @@
case MISCREG_MEPC:
{
auto misa = readMiscRegNoEffect(MISCREG_ISA);
- auto val = readMiscRegNoEffect(misc_reg);
+ auto val = readMiscRegNoEffect(idx);
// if compressed instructions are disabled, epc[1] is set to 0
if ((misa & ISA_EXT_C_MASK) == 0)
return mbits(val, 63, 2);
@@ -342,41 +339,39 @@
default:
// Try reading HPM counters
// As a placeholder, all HPM counters are just cycle counters
- if (misc_reg >= MISCREG_HPMCOUNTER03 &&
- misc_reg <= MISCREG_HPMCOUNTER31) {
- if (hpmCounterEnabled(misc_reg)) {
+ if (idx >= MISCREG_HPMCOUNTER03 &&
+ idx <= MISCREG_HPMCOUNTER31) {
+ if (hpmCounterEnabled(idx)) {
DPRINTF(RiscvMisc, "HPM counter %d: %llu.\n",
- misc_reg - MISCREG_CYCLE,
tc->getCpuPtr()->curCycle());
+ idx - MISCREG_CYCLE, tc->getCpuPtr()->curCycle());
return tc->getCpuPtr()->curCycle();
} else {
- warn("HPM counter %d disabled.\n", misc_reg -
MISCREG_CYCLE);
+ warn("HPM counter %d disabled.\n", idx - MISCREG_CYCLE);
return 0;
}
}
- return readMiscRegNoEffect(misc_reg);
+ return readMiscRegNoEffect(idx);
}
}
void
-ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
+ISA::setMiscRegNoEffect(RegIndex idx, RegVal val)
{
- if (misc_reg > NUM_MISCREGS || misc_reg < 0) {
- // Illegal CSR
- panic("Illegal CSR index %#x\n", misc_reg);
- }
+ // Illegal CSR
+ panic_if(idx > NUM_MISCREGS, "Illegal CSR index %#x\n", idx);
DPRINTF(RiscvMisc, "Setting MiscReg %s (%d) to %#x.\n",
- MiscRegNames[misc_reg], misc_reg, val);
- miscRegFile[misc_reg] = val;
+ MiscRegNames[idx], idx, val);
+ miscRegFile[idx] = val;
}
void
-ISA::setMiscReg(int misc_reg, RegVal val)
+ISA::setMiscReg(RegIndex idx, RegVal val)
{
- if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
+ if (idx >= MISCREG_CYCLE && idx <= MISCREG_HPMCOUNTER31) {
// Ignore writes to HPM counters for now
- warn("Ignoring write to %s.\n", CSRData.at(misc_reg).name);
+ warn("Ignoring write to %s.\n", CSRData.at(idx).name);
} else {
- switch (misc_reg) {
+ switch (idx) {
// From section 3.7.1 of RISCV priv. specs
// V1.12, the odd-numbered configuration
@@ -405,13 +400,13 @@
// Form pmp_index using the index i and
// PMPCFG register number
// Note: MISCREG_PMPCFG2 - MISCREG_PMPCFG0 = 1
- // 8*(misc_reg-MISCREG_PMPCFG0) will be useful
+ // 8*(idx-MISCREG_PMPCFG0) will be useful
// if a system contains more than 16 PMP entries
- uint32_t pmp_index = i+(8*(misc_reg-MISCREG_PMPCFG0));
+ uint32_t pmp_index = i+(8*(idx-MISCREG_PMPCFG0));
mmu->getPMP()->pmpUpdateCfg(pmp_index,cfg_val);
}
- setMiscRegNoEffect(misc_reg, val);
+ setMiscRegNoEffect(idx, val);
}
break;
case MISCREG_PMPADDR00 ... MISCREG_PMPADDR15:
@@ -421,10 +416,10 @@
auto mmu = dynamic_cast<RiscvISA::MMU *>
(tc->getMMUPtr());
- uint32_t pmp_index = misc_reg-MISCREG_PMPADDR00;
+ uint32_t pmp_index = idx-MISCREG_PMPADDR00;
mmu->getPMP()->pmpUpdateAddr(pmp_index, val);
- setMiscRegNoEffect(misc_reg, val);
+ setMiscRegNoEffect(idx, val);
}
break;
@@ -446,43 +441,43 @@
{
// we only support bare and Sv39 mode; setting a different
mode
// shall have no effect (see 4.1.12 in priv ISA manual)
- SATP cur_val = readMiscRegNoEffect(misc_reg);
+ SATP cur_val = readMiscRegNoEffect(idx);
SATP new_val = val;
if (new_val.mode != AddrXlateMode::BARE &&
new_val.mode != AddrXlateMode::SV39)
new_val.mode = cur_val.mode;
- setMiscRegNoEffect(misc_reg, new_val);
+ setMiscRegNoEffect(idx, new_val);
}
break;
case MISCREG_TSELECT:
{
// we don't support debugging, so always set a different
value
// than written
- setMiscRegNoEffect(misc_reg, val + 1);
+ setMiscRegNoEffect(idx, val + 1);
}
break;
case MISCREG_ISA:
{
- auto cur_val = readMiscRegNoEffect(misc_reg);
+ auto cur_val = readMiscRegNoEffect(idx);
// only allow to disable compressed instructions
// if the following instruction is 4-byte aligned
if ((val & ISA_EXT_C_MASK) == 0 &&
bits(tc->pcState().npc(), 2, 0) != 0)
val |= cur_val & ISA_EXT_C_MASK;
- setMiscRegNoEffect(misc_reg, val);
+ setMiscRegNoEffect(idx, val);
}
break;
case MISCREG_STATUS:
{
// SXL and UXL are hard-wired to 64 bit
- auto cur = readMiscRegNoEffect(misc_reg);
+ auto cur = readMiscRegNoEffect(idx);
val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK);
val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
- setMiscRegNoEffect(misc_reg, val);
+ setMiscRegNoEffect(idx, val);
}
break;
default:
- setMiscRegNoEffect(misc_reg, val);
+ setMiscRegNoEffect(idx, val);
}
}
}
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index d68596e..5349da2 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -77,10 +77,10 @@
void clear() override;
public:
- RegVal readMiscRegNoEffect(int misc_reg) const;
- RegVal readMiscReg(int misc_reg);
- void setMiscRegNoEffect(int misc_reg, RegVal val);
- void setMiscReg(int misc_reg, RegVal val);
+ RegVal readMiscRegNoEffect(RegIndex idx) const override;
+ RegVal readMiscReg(RegIndex idx) override;
+ void setMiscRegNoEffect(RegIndex idx, RegVal val) override;
+ void setMiscReg(RegIndex idx, RegVal val) override;
bool inUserMode() const override { return true; }
void copyRegsFrom(ThreadContext *src) override;
diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index 72fe5df..e5f4243 100644
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -38,22 +38,22 @@
namespace gem5
{
+class BaseISA;
+
namespace SparcISA
{
-class ISA;
class Decoder : public InstDecoder
{
protected:
// The extended machine instruction being generated
ExtMachInst emi;
uint32_t machInst;
- bool instDone;
- RegVal asi;
+ bool instDone = false;
+ RegVal asi = 0;
public:
- Decoder(ISA* isa=nullptr) : InstDecoder(&machInst), instDone(false),
asi(0)
- {}
+ Decoder(BaseISA* isa=nullptr) : InstDecoder(&machInst) {}
void process() {}
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index a29d1b9..841989d 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -373,17 +373,17 @@
}
RegVal
-ISA::readMiscRegNoEffect(int miscReg) const
+ISA::readMiscRegNoEffect(RegIndex idx) const
{
- // The three miscRegs are moved up from the switch statement
+ // The three idxs are moved up from the switch statement
// due to more frequent calls.
- if (miscReg == MISCREG_GL)
+ if (idx == MISCREG_GL)
return gl;
- if (miscReg == MISCREG_CWP)
+ if (idx == MISCREG_CWP)
return cwp;
- if (miscReg == MISCREG_TLB_DATA) {
+ if (idx == MISCREG_TLB_DATA) {
/* Package up all the data for the tlb:
* 6666555555555544444444443333333333222222222211111111110000000000
* 3210987654321098765432109876543210987654321098765432109876543210
@@ -405,7 +405,7 @@
(uint64_t)secContext << 48;
}
- switch (miscReg) {
+ switch (idx) {
// case MISCREG_TLB_DATA:
// [original contents see above]
// case MISCREG_Y:
@@ -529,14 +529,14 @@
case MISCREG_QUEUE_NRES_ERROR_TAIL:
return nres_error_tail;
default:
- panic("Miscellaneous register %d not implemented\n", miscReg);
+ panic("Miscellaneous register %d not implemented\n", idx);
}
}
RegVal
-ISA::readMiscReg(int miscReg)
+ISA::readMiscReg(RegIndex idx)
{
- switch (miscReg) {
+ switch (idx) {
// tick and stick are aliased to each other in niagra
// well store the tick data in stick and the interrupt bit in tick
case MISCREG_STICK:
@@ -576,15 +576,15 @@
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
case MISCREG_HPSTATE:
- return readFSReg(miscReg);
+ return readFSReg(idx);
}
- return readMiscRegNoEffect(miscReg);
+ return readMiscRegNoEffect(idx);
}
void
-ISA::setMiscRegNoEffect(int miscReg, RegVal val)
+ISA::setMiscRegNoEffect(RegIndex idx, RegVal val)
{
- switch (miscReg) {
+ switch (idx) {
// case MISCREG_Y:
// y = val;
// break;
@@ -758,16 +758,16 @@
nres_error_tail = val;
break;
default:
- panic("Miscellaneous register %d not implemented\n", miscReg);
+ panic("Miscellaneous register %d not implemented\n", idx);
}
}
void
-ISA::setMiscReg(int miscReg, RegVal val)
+ISA::setMiscReg(RegIndex idx, RegVal val)
{
RegVal new_val = val;
- switch (miscReg) {
+ switch (idx) {
case MISCREG_ASI:
tc->getDecoderPtr()->setContext(val);
break;
@@ -832,10 +832,10 @@
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
case MISCREG_HPSTATE:
- setFSReg(miscReg, val);
+ setFSReg(idx, val);
return;
}
- setMiscRegNoEffect(miscReg, new_val);
+ setMiscRegNoEffect(idx, new_val);
}
void
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index be78975..3176c3b 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -181,11 +181,11 @@
public:
- RegVal readMiscRegNoEffect(int miscReg) const;
- RegVal readMiscReg(int miscReg);
+ RegVal readMiscRegNoEffect(RegIndex idx) const override;
+ RegVal readMiscReg(RegIndex idx) override;
- void setMiscRegNoEffect(int miscReg, RegVal val);
- void setMiscReg(int miscReg, RegVal val);
+ void setMiscRegNoEffect(RegIndex idx, RegVal val) override;
+ void setMiscReg(RegIndex idx, RegVal val) override;
uint64_t
getExecutingAsid() const override
diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index 39fdab9..86b3ef5 100644
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -48,10 +48,11 @@
namespace gem5
{
+class BaseISA;
+
namespace X86ISA
{
-class ISA;
class Decoder : public InstDecoder
{
private:
@@ -255,7 +256,7 @@
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
public:
- Decoder(ISA *isa=nullptr) : InstDecoder(&fetchChunk)
+ Decoder(BaseISA *isa=nullptr) : InstDecoder(&fetchChunk)
{
emi.reset();
emi.mode.mode = mode;
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index d5d92de..8eac1e4 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -202,49 +202,49 @@
}
RegVal
-ISA::readMiscRegNoEffect(int miscReg) const
+ISA::readMiscRegNoEffect(RegIndex idx) const
{
// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else
should
// attempt to read them directly.
- assert(misc_reg::isValid(miscReg));
+ assert(misc_reg::isValid(idx));
- return regVal[miscReg];
+ return regVal[idx];
}
RegVal
-ISA::readMiscReg(int miscReg)
+ISA::readMiscReg(RegIndex idx)
{
- if (miscReg == misc_reg::Tsc) {
+ if (idx == misc_reg::Tsc) {
return regVal[misc_reg::Tsc] + tc->getCpuPtr()->curCycle();
}
- if (miscReg == misc_reg::Fsw) {
+ if (idx == misc_reg::Fsw) {
RegVal fsw = regVal[misc_reg::Fsw];
RegVal top = regVal[misc_reg::X87Top];
return insertBits(fsw, 13, 11, top);
}
- if (miscReg == misc_reg::ApicBase) {
+ if (idx == misc_reg::ApicBase) {
LocalApicBase base = regVal[misc_reg::ApicBase];
base.bsp = (tc->contextId() == 0);
return base;
}
- return readMiscRegNoEffect(miscReg);
+ return readMiscRegNoEffect(idx);
}
void
-ISA::setMiscRegNoEffect(int miscReg, RegVal val)
+ISA::setMiscRegNoEffect(RegIndex idx, RegVal val)
{
// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else
should
// attempt to write to them directly.
- assert(misc_reg::isValid(miscReg));
+ assert(misc_reg::isValid(idx));
HandyM5Reg m5Reg = regVal[misc_reg::M5Reg];
int reg_width = 64;
- switch (miscReg) {
+ switch (idx) {
case misc_reg::X87Top:
reg_width = 3;
break;
@@ -273,18 +273,17 @@
break;
}
- regVal[miscReg] = val & mask(reg_width);
+ regVal[idx] = val & mask(reg_width);
}
void
-ISA::setMiscReg(int miscReg, RegVal val)
+ISA::setMiscReg(RegIndex idx, RegVal val)
{
RegVal newVal = val;
- switch(miscReg)
- {
+ switch (idx) {
case misc_reg::Cr0:
{
- CR0 toggled = regVal[miscReg] ^ val;
+ CR0 toggled = regVal[idx] ^ val;
CR0 newCR0 = val;
Efer efer = regVal[misc_reg::Efer];
if (toggled.pg && efer.lme) {
@@ -318,7 +317,7 @@
break;
case misc_reg::Cr4:
{
- CR4 toggled = regVal[miscReg] ^ val;
+ CR4 toggled = regVal[idx] ^ val;
if (toggled.pae || toggled.pse || toggled.pge) {
tc->getMMUPtr()->flushAll();
}
@@ -328,7 +327,7 @@
break;
case misc_reg::CsAttr:
{
- SegAttr toggled = regVal[miscReg] ^ val;
+ SegAttr toggled = regVal[idx] ^ val;
SegAttr newCSAttr = val;
if (toggled.longMode) {
if (newCSAttr.longMode) {
@@ -366,7 +365,7 @@
case misc_reg::TsgBase:
case misc_reg::TrBase:
case misc_reg::IdtrBase:
- regVal[misc_reg::segEffBase(miscReg - misc_reg::SegBaseBase)] =
val;
+ regVal[misc_reg::segEffBase(idx - misc_reg::SegBaseBase)] = val;
break;
// These segments ignore their bases in 64 bit mode.
// their effective bases must stay equal to their actual bases.
@@ -378,7 +377,7 @@
Efer efer = regVal[misc_reg::Efer];
SegAttr csAttr = regVal[misc_reg::CsAttr];
if (!efer.lma || !csAttr.longMode) // Check for non 64 bit
mode.
- regVal[misc_reg::segEffBase(miscReg -
+ regVal[misc_reg::segEffBase(idx -
misc_reg::SegBaseBase)] = val;
}
break;
@@ -392,7 +391,7 @@
/* These should eventually set up breakpoints. */
break;
case misc_reg::Dr4:
- miscReg = misc_reg::Dr6;
+ idx = misc_reg::Dr6;
[[fallthrough]];
case misc_reg::Dr6:
{
@@ -409,7 +408,7 @@
}
break;
case misc_reg::Dr5:
- miscReg = misc_reg::Dr7;
+ idx = misc_reg::Dr7;
[[fallthrough]];
case misc_reg::Dr7:
{
@@ -467,7 +466,7 @@
default:
break;
}
- setMiscRegNoEffect(miscReg, newVal);
+ setMiscRegNoEffect(idx, newVal);
}
void
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 17dfb4c..7b014b0 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -65,11 +65,11 @@
ISA(const Params &p);
- RegVal readMiscRegNoEffect(int miscReg) const;
- RegVal readMiscReg(int miscReg);
+ RegVal readMiscRegNoEffect(RegIndex idx) const override;
+ RegVal readMiscReg(RegIndex idx) override;
- void setMiscRegNoEffect(int miscReg, RegVal val);
- void setMiscReg(int miscReg, RegVal val);
+ void setMiscRegNoEffect(RegIndex idx, RegVal val) override;
+ void setMiscReg(RegIndex idx, RegVal val) override;
bool
inUserMode() const override
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If706ddf173d4e24d85468fb118b45099acf3c05b
Gerrit-Change-Number: 51237
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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