Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51408 )
Change subject: arch-arm: Use ArmRelease in MMU and TableWalker
......................................................................
arch-arm: Use ArmRelease in MMU and TableWalker
Change-Id: I210c73e0e66390f702dad6e7d737c8271b119091
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/mmu.cc
M src/arch/arm/mmu.hh
M src/arch/arm/ArmMMU.py
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
5 files changed, 42 insertions(+), 24 deletions(-)
diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py
index d32cbff..3a6b921 100644
--- a/src/arch/arm/ArmMMU.py
+++ b/src/arch/arm/ArmMMU.py
@@ -35,6 +35,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+from m5.objects.ArmISA import ArmDefaultSERelease
from m5.objects.ArmTLB import ArmTLB, ArmStage2TLB
from m5.objects.BaseMMU import BaseMMU
from m5.objects.ClockedObject import ClockedObject
@@ -89,6 +90,9 @@
sys = Param.System(Parent.any, "system object parameter")
+ release_se = Param.ArmRelease(ArmDefaultSERelease(),
+ "Set of features/extensions to use in SE mode")
+
@classmethod
def walkerPorts(cls):
return ["mmu.itb_walker.port", "mmu.dtb_walker.port",
diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc
index 52606b0..278a113 100644
--- a/src/arch/arm/mmu.cc
+++ b/src/arch/arm/mmu.cc
@@ -66,21 +66,22 @@
miscRegContext(0),
s1State(this, false), s2State(this, true),
_attr(0),
+ _release(nullptr),
stats(this)
{
// Cache system-level properties
if (FullSystem) {
ArmSystem *arm_sys = dynamic_cast<ArmSystem *>(p.sys);
assert(arm_sys);
- haveLPAE = arm_sys->has(ArmExtension::LPAE);
- haveVirtualization = arm_sys->has(ArmExtension::VIRTUALIZATION);
haveLargeAsid64 = arm_sys->haveLargeAsid64();
physAddrRange = arm_sys->physAddrRange();
+
+ _release = arm_sys->releaseFS();
} else {
- haveLPAE = false;
- haveVirtualization = false;
haveLargeAsid64 = false;
physAddrRange = 48;
+
+ _release = p.release_se;
}
m5opRange = p.sys->m5opRange();
@@ -1238,7 +1239,7 @@
scr = tc->readMiscReg(MISCREG_SCR_EL3);
isPriv = aarch64EL != EL0;
- if (mmu->haveVirtualization) {
+ if (mmu->release()->has(ArmExtension::VIRTUALIZATION)) {
vmid = getVMID(tc);
isHyp = aarch64EL == EL2;
isHyp |= tran_type & HypMode;
@@ -1301,7 +1302,7 @@
!isSecure));
hcr = tc->readMiscReg(MISCREG_HCR);
- if (mmu->haveVirtualization) {
+ if (mmu->release()->has(ArmExtension::VIRTUALIZATION)) {
vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48);
isHyp = cpsr.mode == MODE_HYP;
isHyp |= tran_type & HypMode;
diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index b80968b..7947373 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -327,6 +327,8 @@
_attr = attr;
}
+ const ArmRelease* release() const { return _release; }
+
/**
* Determine the EL to use for the purpose of a translation given
* a specific translation type. If the translation type doesn't
@@ -417,8 +419,7 @@
uint64_t _attr; // Memory attributes for last accessed TLB entry
// Cached copies of system-level properties
- bool haveLPAE;
- bool haveVirtualization;
+ const ArmRelease *_release;
bool haveLargeAsid64;
uint8_t physAddrRange;
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index ba1b4a4..41cdeba 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -65,6 +65,7 @@
isStage2(p.is_stage2), tlb(NULL),
currState(NULL), pending(false),
numSquashable(p.num_squash_per_cycle),
+ release(nullptr),
stats(this),
pendingReqs(0),
pendingChangeTick(curTick()),
@@ -84,13 +85,9 @@
if (FullSystem) {
ArmSystem *arm_sys = dynamic_cast<ArmSystem *>(p.sys);
assert(arm_sys);
- haveSecurity = arm_sys->has(ArmExtension::SECURITY);
- _haveLPAE = arm_sys->has(ArmExtension::LPAE);
- _haveVirtualization = arm_sys->has(ArmExtension::VIRTUALIZATION);
_physAddrRange = arm_sys->physAddrRange();
_haveLargeAsid64 = arm_sys->haveLargeAsid64();
} else {
- haveSecurity = _haveLPAE = _haveVirtualization = false;
_haveLargeAsid64 = false;
_physAddrRange = 48;
}
@@ -117,6 +114,13 @@
return ClockedObject::getPort(if_name, idx);
}
+void
+TableWalker::setMmu(MMU *_mmu)
+{
+ mmu = _mmu;
+ release = mmu->release();
+}
+
TableWalker::WalkerState::WalkerState() :
tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr),
asid(0), vmid(0), isHyp(false), transState(nullptr),
@@ -385,12 +389,12 @@
currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1);
break;
case EL2:
- assert(_haveVirtualization);
+ assert(release->has(ArmExtension::VIRTUALIZATION));
currState->sctlr =
currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
break;
case EL3:
- assert(haveSecurity);
+ assert(release->has(ArmExtension::SECURITY));
currState->sctlr =
currState->tc->readMiscReg(MISCREG_SCTLR_EL3);
currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3);
break;
@@ -576,6 +580,7 @@
// If translation isn't enabled, we shouldn't be here
assert(currState->sctlr.m || isStage2);
const bool is_atomic = currState->req->isAtomic();
+ const bool have_security = release->has(ArmExtension::SECURITY);
DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x,
bits:%#x\n",
currState->vaddr_tainted, currState->ttbcr,
mbits(currState->vaddr, 31,
@@ -587,7 +592,7 @@
32 - currState->ttbcr.n)) {
DPRINTF(TLB, " - Selecting TTBR0\n");
// Check if table walk is allowed when Security Extensions are
enabled
- if (haveSecurity && currState->ttbcr.pd0) {
+ if (have_security && currState->ttbcr.pd0) {
if (currState->isFetch)
return std::make_shared<PrefetchAbort>(
currState->vaddr_tainted,
@@ -607,7 +612,7 @@
} else {
DPRINTF(TLB, " - Selecting TTBR1\n");
// Check if table walk is allowed when Security Extensions are
enabled
- if (haveSecurity && currState->ttbcr.pd1) {
+ if (have_security && currState->ttbcr.pd1) {
if (currState->isFetch)
return std::make_shared<PrefetchAbort>(
currState->vaddr_tainted,
@@ -1451,7 +1456,7 @@
TableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
LongDescriptor &l_descriptor)
{
- assert(_haveLPAE);
+ assert(release->has(ArmExtension::LPAE));
uint8_t attr;
uint8_t sh = l_descriptor.sh();
@@ -2287,6 +2292,7 @@
void
TableWalker::insertTableEntry(DescriptorBase &descriptor, bool
long_descriptor)
{
+ const bool have_security = release->has(ArmExtension::SECURITY);
TlbEntry te;
// Create and fill a new page table entry
@@ -2301,7 +2307,7 @@
te.pfn = descriptor.pfn();
te.domain = descriptor.domain();
te.lookupLevel = descriptor.lookupLevel;
- te.ns = !descriptor.secure(haveSecurity, currState);
+ te.ns = !descriptor.secure(have_security, currState);
te.nstid = !currState->isSecure;
te.xn = descriptor.xn();
te.type = currState->mode == BaseMMU::Execute ?
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 77fb7fc..17cfa12 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -983,9 +983,7 @@
unsigned numSquashable;
/** Cached copies of system-level properties */
- bool haveSecurity;
- bool _haveLPAE;
- bool _haveVirtualization;
+ const ArmRelease *release;
uint8_t _physAddrRange;
bool _haveLargeAsid64;
@@ -1019,8 +1017,6 @@
TableWalker(const Params &p);
virtual ~TableWalker();
- bool haveLPAE() const { return _haveLPAE; }
- bool haveVirtualization() const { return _haveVirtualization; }
bool haveLargeAsid64() const { return _haveLargeAsid64; }
uint8_t physAddrRange() const { return _physAddrRange; }
/** Checks if all state is cleared and if so, completes drain */
@@ -1039,7 +1035,7 @@
bool timing, bool functional, bool secure,
MMU::ArmTranslationType tranType, bool _stage2Req);
- void setMmu(MMU *_mmu) { mmu = _mmu; }
+ void setMmu(MMU *_mmu);
void setTlb(TLB *_tlb) { tlb = _tlb; }
TLB* getTlb() { return tlb; }
void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51408
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I210c73e0e66390f702dad6e7d737c8271b119091
Gerrit-Change-Number: 51408
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
