Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51448 )
Change subject: python: Generalize ruby components in library
......................................................................
python: Generalize ruby components in library
The Ruby protocols in the components library had some special cases for
x86 that ended up breaking other ISAs (RISC-V in my testing). This
change generalizes those scripts slightly so they will work with both
x86 and RISC-V
Change-Id: I32afa3dc6131ab3751150746f0b2c63ba4a168c6
Signed-off-by: Jason Lowe-Power <[email protected]>
---
M
src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
M
src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
2 files changed, 29 insertions(+), 28 deletions(-)
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
index e5d0353..9d42365 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
@@ -110,21 +110,14 @@
board.get_clock_domain(),
)
+ cache.sequencer = RubySequencer(
+ version=i,
+ dcache=cache.L1Dcache,
+ clk_domain=cache.clk_domain,
+ )
+
if board.has_io_bus():
- cache.sequencer = RubySequencer(
- version=i,
- dcache=cache.L1Dcache,
- clk_domain=cache.clk_domain,
- pio_request_port=board.get_io_bus().cpu_side_ports,
- mem_request_port=board.get_io_bus().cpu_side_ports,
- pio_response_port=board.get_io_bus().mem_side_ports,
- )
- else:
- cache.sequencer = RubySequencer(
- version=i,
- dcache=cache.L1Dcache,
- clk_domain=cache.clk_domain,
- )
+ cache.sequencer.connectIOPorts(board.get_io_bus())
cache.ruby_system = self.ruby_system
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
index 338d1c4..523ba49 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
@@ -97,21 +97,14 @@
clk_domain=board.get_clock_domain(),
)
+ cache.sequencer = RubySequencer(
+ version=i,
+ dcache=cache.cacheMemory,
+ clk_domain=cache.clk_domain,
+ )
+
if board.has_io_bus():
- cache.sequencer = RubySequencer(
- version=i,
- dcache=cache.cacheMemory,
- clk_domain=cache.clk_domain,
- pio_request_port=board.get_io_bus().cpu_side_ports,
- mem_request_port=board.get_io_bus().cpu_side_ports,
- pio_response_port=board.get_io_bus().mem_side_ports,
- )
- else:
- cache.sequencer = RubySequencer(
- version=i,
- dcache=cache.L1Dcache,
- clk_domain=cache.clk_domain,
- )
+ cache.sequencer.connectIOPorts(board.get_io_bus())
cache.ruby_system = self.ruby_system
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I32afa3dc6131ab3751150746f0b2c63ba4a168c6
Gerrit-Change-Number: 51448
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: newchange
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