Mahyar Samani has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51609 )
Change subject: mem: Adding PortTerminator
......................................................................
mem: Adding PortTerminator
This change adds the source code for the PortTerminator SimObject.
It could be used to connect request/response ports in the system
that can not be connected to any other ports. This will prevent
errors caused by orphan ports in the system.
Change-Id: I5e19cdd3ce064638ffabf29d29225eda77ffc146
---
A src/mem/PortTerminator.py
A src/mem/port_terminator.cc
A src/mem/port_terminator.hh
M src/mem/SConscript
4 files changed, 240 insertions(+), 0 deletions(-)
diff --git a/src/mem/PortTerminator.py b/src/mem/PortTerminator.py
new file mode 100644
index 0000000..d0b7169
--- /dev/null
+++ b/src/mem/PortTerminator.py
@@ -0,0 +1,53 @@
+# Copyright (c) 2012-2021 Arm Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2013 Amin Farmahini-Farahani
+# Copyright (c) 2015 University of Kaiserslautern
+# Copyright (c) 2015 The University of Bologna
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.params import *
+from m5.SimObject import SimObject
+
+class PortTerminator(SimObject):
+ type = 'PortTerminator'
+ abstract = False
+ cxx_header = "mem/port_terminator.hh"
+ cxx_class = 'gem5::PortTerminator'
+
+ req_ports = VectorRequestPort("Vector port for connecting terminating "
+ "response ports.")
+ resp_ports = VectorResponsePort("Vector port for terminating "
+ "request ports.")
\ No newline at end of file
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 5d3c5e6..e200982 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -58,6 +58,7 @@
SimObject('HMCController.py')
SimObject('SerialLink.py')
SimObject('MemDelay.py')
+SimObject('PortTerminator.py')
Source('abstract_mem.cc')
Source('addr_mapper.cc')
@@ -85,6 +86,7 @@
Source('htm.cc')
Source('serial_link.cc')
Source('mem_delay.cc')
+Source('port_terminator.cc')
if env['TARGET_ISA'] != 'null':
Source('translating_port_proxy.cc')
diff --git a/src/mem/port_terminator.cc b/src/mem/port_terminator.cc
new file mode 100644
index 0000000..cd56c53
--- /dev/null
+++ b/src/mem/port_terminator.cc
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/port_terminator.hh"
+
+namespace gem5 {
+
+PortTerminator::PortTerminator(const PortTerminatorParams ¶ms):
+ SimObject(params),
+ nReqPorts(params.port_req_ports_connection_count),
+ nRespPorts(params.port_resp_ports_connection_count)
+{
+ for (int i = 0; i < nReqPorts; ++i) {
+ reqPorts.emplace_back(name() + ".req_ports" + std::to_string(i),
this);
+ }
+ for (int j = 0; j < nRespPorts; ++j) {
+ reqPorts.emplace_back(name() + ".resp_ports" +
+ std::to_string(j), this);
+ }
+}
+
+Port &
+PortTerminator::getPort(const std::string &if_name, PortID idx)
+{
+ if (if_name == "req_ports" && idx < nReqPorts) {
+ return reqPorts[idx];
+ } else if (if_name == "resp_ports" && idx < nRespPorts) {
+ return respPorts[idx];
+ } else {
+ // pass it along to our super class
+ return SimObject::getPort(if_name, idx);
+ }
+}
+
+}
\ No newline at end of file
diff --git a/src/mem/port_terminator.hh b/src/mem/port_terminator.hh
new file mode 100644
index 0000000..80e29e3
--- /dev/null
+++ b/src/mem/port_terminator.hh
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <vector>
+
+#include "mem/port.hh"
+#include "params/PortTerminator.hh"
+#include "sim/sim_object.hh"
+
+namespace gem5
+{
+
+class PortTerminator : public SimObject
+{
+private:
+ class ReqPort : public RequestPort
+ {
+ public:
+ ReqPort(const std::string &name, PortTerminator *owner):
+ RequestPort(name, owner)
+ {}
+ protected:
+ bool recvTimingResp(PacketPtr pkt) override
+ {
+ return true;
+ }
+
+ void recvReqRetry() override
+ {
+ return;
+ }
+
+ void recvRangeChange() override
+ {
+ return;
+ }
+ };
+
+ class RespPort : public ResponsePort
+ {
+ public:
+ RespPort(const std::string &name, PortTerminator *owner):
+ ResponsePort(name, owner)
+ {}
+ };
+
+ std::vector<ReqPort> reqPorts;
+
+ std::vector<RespPort> respPorts;
+
+ int nReqPorts;
+
+ int nRespPorts;
+
+public:
+ PortTerminator(const PortTerminatorParams ¶ms);
+ /** A function used to return the port associated with this object. */
+ Port &getPort(const std::string &if_name,
+ PortID idx = InvalidPortID) override;
+};
+
+}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5e19cdd3ce064638ffabf29d29225eda77ffc146
Gerrit-Change-Number: 51609
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani <[email protected]>
Gerrit-MessageType: newchange
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