Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51670 )
Change subject: arch-arm: Use EL2&0 regime for invalidation only if EL2
enabled
......................................................................
arch-arm: Use EL2&0 regime for invalidation only if EL2 enabled
Change-Id: I467a27e48d077cea5e56afae08f9e0e72f529cfc
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/isa.cc
1 file changed, 74 insertions(+), 24 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ccec453..3421ce9 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1933,10 +1933,15 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- HCR hcr = readMiscReg(MISCREG_HCR_EL2);
- bool is_host = (hcr.tge && hcr.e2h);
+ ExceptionLevel target_el = EL1;
+ if (EL2Enabled(tc)) {
+ HCR hcr = readMiscReg(MISCREG_HCR_EL2);
+ if (hcr.tge && hcr.e2h) {
+ target_el = EL2;
+ }
+ }
+
bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
- ExceptionLevel target_el = is_host ? EL2 : EL1;
TLBIVMALL tlbiOp(target_el, secure, false);
tlbiOp(tc);
return;
@@ -1956,10 +1961,15 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- HCR hcr = readMiscReg(MISCREG_HCR_EL2);
- bool is_host = (hcr.tge && hcr.e2h);
+ ExceptionLevel target_el = EL1;
+ if (EL2Enabled(tc)) {
+ HCR hcr = readMiscReg(MISCREG_HCR_EL2);
+ if (hcr.tge && hcr.e2h) {
+ target_el = EL2;
+ }
+ }
+
bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
- ExceptionLevel target_el = is_host ? EL2 : EL1;
TLBIVMALL tlbiOp(target_el, secure, false);
tlbiOp.broadcast(tc);
return;
@@ -2051,10 +2061,15 @@
auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
bits(newVal, 55, 48);
- HCR hcr = readMiscReg(MISCREG_HCR_EL2);
- bool is_host = (hcr.tge && hcr.e2h);
+ ExceptionLevel target_el = EL1;
+ if (EL2Enabled(tc)) {
+ HCR hcr = readMiscReg(MISCREG_HCR_EL2);
+ if (hcr.tge && hcr.e2h) {
+ target_el = EL2;
+ }
+ }
+
bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
- ExceptionLevel target_el = is_host ? EL2 : EL1;
TLBIMVA tlbiOp(target_el, secure,
static_cast<Addr>(bits(newVal, 43, 0)) <<
12,
asid);
@@ -2071,10 +2086,15 @@
auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
bits(newVal, 55, 48);
- HCR hcr = readMiscReg(MISCREG_HCR_EL2);
- bool is_host = (hcr.tge && hcr.e2h);
+ ExceptionLevel target_el = EL1;
+ if (EL2Enabled(tc)) {
+ HCR hcr = readMiscReg(MISCREG_HCR_EL2);
+ if (hcr.tge && hcr.e2h) {
+ target_el = EL2;
+ }
+ }
+
bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
- ExceptionLevel target_el = is_host ? EL2 : EL1;
TLBIMVA tlbiOp(target_el, secure,
static_cast<Addr>(bits(newVal, 43, 0)) <<
12,
asid);
@@ -2090,10 +2110,15 @@
auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
bits(newVal, 55, 48);
- HCR hcr = readMiscReg(MISCREG_HCR_EL2);
- bool is_host = (hcr.tge && hcr.e2h);
+ ExceptionLevel target_el = EL1;
+ if (EL2Enabled(tc)) {
+ HCR hcr = readMiscReg(MISCREG_HCR_EL2);
+ if (hcr.tge && hcr.e2h) {
+ target_el = EL2;
+ }
+ }
+
bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
- ExceptionLevel target_el = is_host ? EL2 : EL1;
TLBIASID tlbiOp(target_el, secure, asid);
tlbiOp(tc);
return;
@@ -2106,10 +2131,15 @@
auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
bits(newVal, 55, 48);
- HCR hcr = readMiscReg(MISCREG_HCR_EL2);
- bool is_host = (hcr.tge && hcr.e2h);
+ ExceptionLevel target_el = EL1;
+ if (EL2Enabled(tc)) {
+ HCR hcr = readMiscReg(MISCREG_HCR_EL2);
+ if (hcr.tge && hcr.e2h) {
+ target_el = EL2;
+ }
+ }
+
bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
- ExceptionLevel target_el = is_host ? EL2 : EL1;
TLBIASID tlbiOp(target_el, secure, asid);
tlbiOp.broadcast(tc);
return;
@@ -2123,10 +2153,15 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- HCR hcr = readMiscReg(MISCREG_HCR_EL2);
- bool is_host = (hcr.tge && hcr.e2h);
+ ExceptionLevel target_el = EL1;
+ if (EL2Enabled(tc)) {
+ HCR hcr = readMiscReg(MISCREG_HCR_EL2);
+ if (hcr.tge && hcr.e2h) {
+ target_el = EL2;
+ }
+ }
+
bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
- ExceptionLevel target_el = is_host ? EL2 : EL1;
TLBIMVAA tlbiOp(target_el, secure,
static_cast<Addr>(bits(newVal, 43, 0)) << 12);
@@ -2140,10 +2175,15 @@
assert64();
scr = readMiscReg(MISCREG_SCR);
- HCR hcr = readMiscReg(MISCREG_HCR_EL2);
- bool is_host = (hcr.tge && hcr.e2h);
+ ExceptionLevel target_el = EL1;
+ if (EL2Enabled(tc)) {
+ HCR hcr = readMiscReg(MISCREG_HCR_EL2);
+ if (hcr.tge && hcr.e2h) {
+ target_el = EL2;
+ }
+ }
+
bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
- ExceptionLevel target_el = is_host ? EL2 : EL1;
TLBIMVAA tlbiOp(target_el, secure,
static_cast<Addr>(bits(newVal, 43, 0)) << 12);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I467a27e48d077cea5e56afae08f9e0e72f529cfc
Gerrit-Change-Number: 51670
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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