Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51667 )
Change subject: arch-arm: Do not always print 0 stats in ArmTLB
......................................................................
arch-arm: Do not always print 0 stats in ArmTLB
We shouldn't print all TLB stats regardless of their value
For example there is no need to print the number of
read/write hits/misses/accesses in a instruction only TLB as
it will always inevitably be zero
With this patch we are flagging them as nozero, in order
to suppress their printing in the final stats file.
We are still printing them (regardless of their value) in the
unified TLB type
Change-Id: I54e57d856ceb451f6bacdd175a61768d030862aa
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
2 files changed, 59 insertions(+), 13 deletions(-)
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 9143723..d804a0f 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -62,7 +62,7 @@
: BaseTLB(p), table(new TlbEntry[p.size]), size(p.size),
isStage2(p.is_stage2),
tableWalker(nullptr),
- stats(this), rangeMRU(1), vmid(0)
+ stats(*this), rangeMRU(1), vmid(0)
{
}
@@ -545,14 +545,14 @@
{
}
-TLB::TlbStats::TlbStats(statistics::Group *parent)
- : statistics::Group(parent),
- ADD_STAT(instHits, statistics::units::Count::get(), "ITB inst hits"),
- ADD_STAT(instMisses, statistics::units::Count::get(), "ITB inst
misses"),
- ADD_STAT(readHits, statistics::units::Count::get(), "DTB read hits"),
- ADD_STAT(readMisses, statistics::units::Count::get(), "DTB read
misses"),
- ADD_STAT(writeHits, statistics::units::Count::get(), "DTB write hits"),
- ADD_STAT(writeMisses, statistics::units::Count::get(), "DTB write
misses"),
+TLB::TlbStats::TlbStats(TLB &parent)
+ : statistics::Group(&parent), tlb(parent),
+ ADD_STAT(instHits, statistics::units::Count::get(), "Inst hits"),
+ ADD_STAT(instMisses, statistics::units::Count::get(), "Inst misses"),
+ ADD_STAT(readHits, statistics::units::Count::get(), "Read hits"),
+ ADD_STAT(readMisses, statistics::units::Count::get(), "Read misses"),
+ ADD_STAT(writeHits, statistics::units::Count::get(), "Write hits"),
+ ADD_STAT(writeMisses, statistics::units::Count::get(), "Write misses"),
ADD_STAT(inserts, statistics::units::Count::get(),
"Number of times an entry is inserted into the TLB"),
ADD_STAT(flushTlb, statistics::units::Count::get(),
@@ -565,11 +565,11 @@
"Number of times TLB was flushed by ASID"),
ADD_STAT(flushedEntries, statistics::units::Count::get(),
"Number of entries that have been flushed from TLB"),
- ADD_STAT(readAccesses, statistics::units::Count::get(), "DTB read
accesses",
+ ADD_STAT(readAccesses, statistics::units::Count::get(), "Read
accesses",
readHits + readMisses),
- ADD_STAT(writeAccesses, statistics::units::Count::get(), "DTB write
accesses",
+ ADD_STAT(writeAccesses, statistics::units::Count::get(), "Write
accesses",
writeHits + writeMisses),
- ADD_STAT(instAccesses, statistics::units::Count::get(), "ITB inst
accesses",
+ ADD_STAT(instAccesses, statistics::units::Count::get(), "Inst
accesses",
instHits + instMisses),
ADD_STAT(hits, statistics::units::Count::get(),
"Total TLB (inst and data) hits",
@@ -581,6 +581,28 @@
"Total TLB (inst and data) accesses",
readAccesses + writeAccesses + instAccesses)
{
+ // If this is a pure Data TLB, mark the instruction
+ // stats as nozero, so that they won't make it in
+ // into the final stats file
+ if (tlb.type() == TypeTLB::data) {
+ instHits.flags(nozero);
+ instMisses.flags(nozero);
+
+ instAccesses.flags(nozero);
+ }
+
+ // If this is a pure Instruction TLB, mark the data
+ // stats as nozero, so that they won't make it in
+ // into the final stats file
+ if (tlb.type() & TypeTLB::instruction) {
+ readHits.flags(nozero);
+ readMisses.flags(nozero);
+ writeHits.flags(nozero);
+ writeMisses.flags(nozero);
+
+ readAccesses.flags(nozero);
+ writeAccesses.flags(nozero);
+ }
}
void
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 4b3c829..c4b5eb7 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -123,7 +123,10 @@
struct TlbStats : public statistics::Group
{
- TlbStats(statistics::Group *parent);
+ TlbStats(TLB &parent);
+
+ const TLB &tlb;
+
// Access Stats
mutable statistics::Scalar instHits;
mutable statistics::Scalar instMisses;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I54e57d856ceb451f6bacdd175a61768d030862aa
Gerrit-Change-Number: 51667
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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