Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51668 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: EL2/EL3 TLB invalidations should ignore the ASID
......................................................................
arch-arm: EL2/EL3 TLB invalidations should ignore the ASID
By using the TLBIMVAA class we invalidate for every ASID
Change-Id: Ie53747067275b01eab42d49b5fa518334a86ac53
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51668
Tested-by: kokoro <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa.cc
1 file changed, 51 insertions(+), 14 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 834dcca..ccec453 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1973,9 +1973,8 @@
{
assert64();
- TLBIMVA tlbiOp(EL3, true,
- static_cast<Addr>(bits(newVal, 43, 0)) <<
12,
- 0xbeef);
+ TLBIMVAA tlbiOp(EL3, true,
+ static_cast<Addr>(bits(newVal, 43, 0)) <<
12);
tlbiOp(tc);
return;
}
@@ -1985,9 +1984,8 @@
{
assert64();
- TLBIMVA tlbiOp(EL3, true,
- static_cast<Addr>(bits(newVal, 43, 0)) <<
12,
- 0xbeef);
+ TLBIMVAA tlbiOp(EL3, true,
+ static_cast<Addr>(bits(newVal, 43, 0)) <<
12);
tlbiOp.broadcast(tc);
return;
@@ -1998,12 +1996,24 @@
{
assert64();
scr = readMiscReg(MISCREG_SCR);
+ HCR hcr = readMiscReg(MISCREG_HCR_EL2);
bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
- TLBIMVA tlbiOp(EL2, secure,
- static_cast<Addr>(bits(newVal, 43, 0)) <<
12,
- 0xbeef);
- tlbiOp(tc);
+
+ if (hcr.e2h) {
+ // The asid will only be used when e2h == 1
+ auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
+ bits(newVal, 55, 48);
+
+ TLBIMVA tlbiOp(EL2, secure,
+ static_cast<Addr>(bits(newVal, 43, 0))
<< 12,
+ asid);
+ tlbiOp(tc);
+ } else {
+ TLBIMVAA tlbiOp(EL2, secure,
+ static_cast<Addr>(bits(newVal, 43, 0))
<< 12);
+ tlbiOp(tc);
+ }
return;
}
// AArch64 TLB Invalidate by VA, EL2, Inner Shareable
@@ -2012,13 +2022,24 @@
{
assert64();
scr = readMiscReg(MISCREG_SCR);
+ HCR hcr = readMiscReg(MISCREG_HCR_EL2);
bool secure = release->has(ArmExtension::SECURITY)
&& !scr.ns;
- TLBIMVA tlbiOp(EL2, secure,
- static_cast<Addr>(bits(newVal, 43, 0)) <<
12,
- 0xbeef);
- tlbiOp.broadcast(tc);
+ if (hcr.e2h) {
+ // The asid will only be used when e2h == 1
+ auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
+ bits(newVal, 55, 48);
+
+ TLBIMVA tlbiOp(EL2, secure,
+ static_cast<Addr>(bits(newVal, 43, 0))
<< 12,
+ asid);
+ tlbiOp.broadcast(tc);
+ } else {
+ TLBIMVAA tlbiOp(EL2, secure,
+ static_cast<Addr>(bits(newVal, 43, 0))
<< 12);
+ tlbiOp.broadcast(tc);
+ }
return;
}
// AArch64 TLB Invalidate by VA, EL1
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie53747067275b01eab42d49b5fa518334a86ac53
Gerrit-Change-Number: 51668
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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