Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50761 )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch: Make the MMU ranged translateFunction pure virtual.
......................................................................
arch: Make the MMU ranged translateFunction pure virtual.
The (simple) implementation in each ISAs MMU can then specify the page
size it wants, which is the page size appropriate for that ISA.
Change-Id: Ia105150601595bd6bb34379fc59508d0ffe35243
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50761
Tested-by: kokoro <[email protected]>
Maintainer: Gabe Black <[email protected]>
Reviewed-by: Daniel Carvalho <[email protected]>
---
M src/arch/sparc/mmu.hh
M src/arch/arm/mmu.hh
M src/arch/riscv/mmu.hh
M src/arch/mips/mmu.hh
M src/arch/x86/mmu.hh
M src/arch/generic/mmu.cc
M src/arch/generic/mmu.hh
M src/arch/power/mmu.hh
8 files changed, 71 insertions(+), 12 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index 03660e4..9391612 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -41,6 +41,7 @@
#ifndef __ARCH_ARM_MMU_HH__
#define __ARCH_ARM_MMU_HH__
+#include "arch/arm/page_size.hh"
#include "arch/arm/tlb.hh"
#include "arch/generic/mmu.hh"
@@ -81,6 +82,14 @@
TableWalker *dtbStage2Walker;
public:
+ TranslationGenPtr
+ translateFunctional(Addr start, Addr size, ThreadContext *tc,
+ Mode mode, Request::Flags flags) override
+ {
+ return TranslationGenPtr(new MMUTranslationGen(
+ PageBytes, start, size, tc, this, mode, flags));
+ }
+
enum ArmFlags
{
AlignmentMask = 0x7,
diff --git a/src/arch/generic/mmu.cc b/src/arch/generic/mmu.cc
index 3d1de81..a765228 100644
--- a/src/arch/generic/mmu.cc
+++ b/src/arch/generic/mmu.cc
@@ -153,15 +153,6 @@
range.paddr = req->getPaddr();
}
-TranslationGenPtr
-BaseMMU::translateFunctional(Addr start, Addr size, ThreadContext *tc,
- BaseMMU::Mode mode, Request::Flags flags)
-{
- return TranslationGenPtr(new MMUTranslationGen(
- tc->getSystemPtr()->getPageBytes(), start, size, tc, this,
- mode, flags));
-}
-
void
BaseMMU::takeOverFrom(BaseMMU *old_mmu)
{
diff --git a/src/arch/generic/mmu.hh b/src/arch/generic/mmu.hh
index 532b591..d090f6d 100644
--- a/src/arch/generic/mmu.hh
+++ b/src/arch/generic/mmu.hh
@@ -146,7 +146,7 @@
* instead of directly translating a specific address.
*/
virtual TranslationGenPtr translateFunctional(Addr start, Addr size,
- ThreadContext *tc, BaseMMU::Mode mode, Request::Flags flags);
+ ThreadContext *tc, BaseMMU::Mode mode, Request::Flags flags) =
0;
virtual Fault
finalizePhysical(const RequestPtr &req, ThreadContext *tc,
diff --git a/src/arch/mips/mmu.hh b/src/arch/mips/mmu.hh
index 13ea937..f20c99c 100644
--- a/src/arch/mips/mmu.hh
+++ b/src/arch/mips/mmu.hh
@@ -39,7 +39,7 @@
#define __ARCH_MIPS_MMU_HH__
#include "arch/generic/mmu.hh"
-
+#include "arch/mips/page_size.hh"
#include "params/MipsMMU.hh"
namespace gem5
@@ -53,6 +53,14 @@
MMU(const MipsMMUParams &p)
: BaseMMU(p)
{}
+
+ TranslationGenPtr
+ translateFunctional(Addr start, Addr size, ThreadContext *tc,
+ Mode mode, Request::Flags flags) override
+ {
+ return TranslationGenPtr(new MMUTranslationGen(
+ PageBytes, start, size, tc, this, mode, flags));
+ }
};
} // namespace MipsISA
diff --git a/src/arch/power/mmu.hh b/src/arch/power/mmu.hh
index 8507e4e..c82ced9 100644
--- a/src/arch/power/mmu.hh
+++ b/src/arch/power/mmu.hh
@@ -39,7 +39,7 @@
#define __ARCH_POWER_MMU_HH__
#include "arch/generic/mmu.hh"
-
+#include "arch/power/page_size.hh"
#include "params/PowerMMU.hh"
namespace gem5
@@ -53,6 +53,14 @@
MMU(const PowerMMUParams &p)
: BaseMMU(p)
{}
+
+ TranslationGenPtr
+ translateFunctional(Addr start, Addr size, ThreadContext *tc,
+ Mode mode, Request::Flags flags) override
+ {
+ return TranslationGenPtr(new MMUTranslationGen(
+ PageBytes, start, size, tc, this, mode, flags));
+ }
};
} // namespace PowerISA
diff --git a/src/arch/riscv/mmu.hh b/src/arch/riscv/mmu.hh
index b0e645c..f8afaa7 100644
--- a/src/arch/riscv/mmu.hh
+++ b/src/arch/riscv/mmu.hh
@@ -40,6 +40,7 @@
#include "arch/generic/mmu.hh"
#include "arch/riscv/isa.hh"
+#include "arch/riscv/page_size.hh"
#include "arch/riscv/pma_checker.hh"
#include "arch/riscv/tlb.hh"
@@ -59,6 +60,14 @@
: BaseMMU(p), pma(p.pma_checker)
{}
+ TranslationGenPtr
+ translateFunctional(Addr start, Addr size, ThreadContext *tc,
+ Mode mode, Request::Flags flags) override
+ {
+ return TranslationGenPtr(new MMUTranslationGen(
+ PageBytes, start, size, tc, this, mode, flags));
+ }
+
PrivilegeMode
getMemPriv(ThreadContext *tc, BaseMMU::Mode mode)
{
diff --git a/src/arch/sparc/mmu.hh b/src/arch/sparc/mmu.hh
index c9bb539..e80f08d 100644
--- a/src/arch/sparc/mmu.hh
+++ b/src/arch/sparc/mmu.hh
@@ -39,6 +39,7 @@
#define __ARCH_SPARC_MMU_HH__
#include "arch/generic/mmu.hh"
+#include "arch/sparc/page_size.hh"
#include "arch/sparc/tlb.hh"
#include "params/SparcMMU.hh"
@@ -55,6 +56,14 @@
: BaseMMU(p)
{}
+ TranslationGenPtr
+ translateFunctional(Addr start, Addr size, ThreadContext *tc,
+ Mode mode, Request::Flags flags) override
+ {
+ return TranslationGenPtr(new MMUTranslationGen(
+ PageBytes, start, size, tc, this, mode, flags));
+ }
+
void
insertItlbEntry(Addr vpn, int partition_id, int context_id, bool real,
const PageTableEntry& PTE, int entry=-1)
diff --git a/src/arch/x86/mmu.hh b/src/arch/x86/mmu.hh
index 3f53863..5dcba94 100644
--- a/src/arch/x86/mmu.hh
+++ b/src/arch/x86/mmu.hh
@@ -39,6 +39,7 @@
#define __ARCH_X86_MMU_HH__
#include "arch/generic/mmu.hh"
+#include "arch/x86/page_size.hh"
#include "arch/x86/tlb.hh"
#include "params/X86MMU.hh"
@@ -67,6 +68,14 @@
{
return static_cast<TLB*>(dtb)->getWalker();
}
+
+ TranslationGenPtr
+ translateFunctional(Addr start, Addr size, ThreadContext *tc,
+ Mode mode, Request::Flags flags) override
+ {
+ return TranslationGenPtr(new MMUTranslationGen(
+ PageBytes, start, size, tc, this, mode, flags));
+ }
};
} // namespace X86ISA
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50761
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia105150601595bd6bb34379fc59508d0ffe35243
Gerrit-Change-Number: 50761
Gerrit-PatchSet: 14
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Matthew Poremba <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
