Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52042 )
Change subject: arch,cpu,sim: Use PCState * and & to trace and not
TheISA::PCState.
......................................................................
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
Change-Id: Ia31919ef19f973aa7af973889366412f3999342a
---
M src/arch/arm/tracers/tarmac_record_v8.hh
M src/cpu/inst_pb_trace.cc
M src/cpu/inst_pb_trace.hh
M src/cpu/exetrace.cc
M src/cpu/exetrace.hh
M src/sim/insttracer.hh
M src/cpu/inteltrace.cc
M src/cpu/inteltrace.hh
M src/cpu/nativetrace.hh
M src/arch/arm/tracers/tarmac_record.cc
M src/arch/arm/tracers/tarmac_record.hh
M src/arch/arm/tracers/tarmac_base.cc
M src/arch/arm/tracers/tarmac_base.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_parser.hh
M src/arch/arm/tracers/tarmac_tracer.cc
M src/arch/arm/tracers/tarmac_tracer.hh
17 files changed, 100 insertions(+), 83 deletions(-)
diff --git a/src/arch/arm/tracers/tarmac_base.cc
b/src/arch/arm/tracers/tarmac_base.cc
index d0f0bcd..c8a8619 100644
--- a/src/arch/arm/tracers/tarmac_base.cc
+++ b/src/arch/arm/tracers/tarmac_base.cc
@@ -54,7 +54,7 @@
TarmacBaseRecord::TarmacBaseRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst,
- PCState _pc,
+ const PCStateBase &_pc,
const StaticInstPtr _macroStaticInst)
: InstRecord(_when, _thread, _staticInst, _pc, _macroStaticInst)
{
@@ -62,7 +62,7 @@
TarmacBaseRecord::InstEntry::InstEntry(
ThreadContext* thread,
- PCState pc,
+ const PCStateBase &pc,
const StaticInstPtr staticInst,
bool predicate)
: taken(predicate) ,
@@ -83,7 +83,7 @@
[](char& c) { c = toupper(c); });
}
-TarmacBaseRecord::RegEntry::RegEntry(PCState pc)
+TarmacBaseRecord::RegEntry::RegEntry(const PCStateBase &pc)
: isetstate(pcToISetState(pc)),
values(2, 0)
{
@@ -100,15 +100,16 @@
}
TarmacBaseRecord::ISetState
-TarmacBaseRecord::pcToISetState(PCState pc)
+TarmacBaseRecord::pcToISetState(const PCStateBase &pc)
{
+ auto &apc = pc.as<ArmISA::PCState>();
TarmacBaseRecord::ISetState isetstate;
- if (pc.aarch64())
+ if (apc.aarch64())
isetstate = TarmacBaseRecord::ISET_A64;
- else if (!pc.thumb() && !pc.jazelle())
+ else if (!apc.thumb() && !apc.jazelle())
isetstate = TarmacBaseRecord::ISET_ARM;
- else if (pc.thumb() && !pc.jazelle())
+ else if (apc.thumb() && !apc.jazelle())
isetstate = TarmacBaseRecord::ISET_THUMB;
else
// No Jazelle state in TARMAC
diff --git a/src/arch/arm/tracers/tarmac_base.hh
b/src/arch/arm/tracers/tarmac_base.hh
index a29eb74..cbf87a3 100644
--- a/src/arch/arm/tracers/tarmac_base.hh
+++ b/src/arch/arm/tracers/tarmac_base.hh
@@ -85,7 +85,7 @@
{
InstEntry() = default;
InstEntry(ThreadContext* thread,
- ArmISA::PCState pc,
+ const PCStateBase &pc,
const StaticInstPtr staticInst,
bool predicate);
@@ -109,7 +109,7 @@
};
RegEntry() = default;
- RegEntry(ArmISA::PCState pc);
+ RegEntry(const PCStateBase &pc);
RegType type;
RegIndex index;
@@ -130,8 +130,8 @@
public:
TarmacBaseRecord(Tick _when, ThreadContext *_thread,
- const StaticInstPtr _staticInst, ArmISA::PCState _pc,
- const StaticInstPtr _macroStaticInst = NULL);
+ const StaticInstPtr _staticInst, const PCStateBase
&_pc,
+ const StaticInstPtr _macroStaticInst=nullptr);
virtual void dump() = 0;
@@ -142,7 +142,7 @@
* @param pc program counter (PCState) variable
* @return Instruction Set State for the given PCState
*/
- static ISetState pcToISetState(ArmISA::PCState pc);
+ static ISetState pcToISetState(const PCStateBase &pc);
};
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index e955314..45a6332 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -918,7 +918,7 @@
if (!same) {
if (!mismatch) {
- TarmacParserRecord::printMismatchHeader(inst, pc);
+ TarmacParserRecord::printMismatchHeader(inst, *pc);
mismatch = true;
}
outs << "diff> [" << it->repr << "] gem5: 0x" << std::hex;
@@ -951,21 +951,21 @@
void
TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst,
- ArmISA::PCState pc)
+ const PCStateBase &pc)
{
std::ostream &outs = Trace::output();
outs << "\nMismatch between gem5 and TARMAC trace @ " << std::dec
<< curTick() << " ticks\n"
<< "[seq_num: " << std::dec << instRecord.seq_num
<< ", opcode: 0x" << std::hex << (staticInst->getEMI() &
0xffffffff)
- << ", PC: 0x" << pc.pc()
- << ", disasm: " << staticInst->disassemble(pc.pc()) << "]"
+ << ", PC: 0x" << pc.instAddr()
+ << ", disasm: " << staticInst->disassemble(pc.instAddr()) << "]"
<< std::endl;
}
TarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst,
- PCState _pc,
+ const PCStateBase &_pc,
TarmacParser& _parent,
const StaticInstPtr
_macroStaticInst)
: TarmacBaseRecord(_when, _thread, _staticInst,
@@ -1008,10 +1008,10 @@
case TARMAC_INST:
parsingStarted = true;
- if (pc.instAddr() != instRecord.addr) {
+ if (pc->instAddr() != instRecord.addr) {
if (!mismatch)
- printMismatchHeader(staticInst, pc);
- outs << "diff> [PC] gem5: 0x" << std::hex <<
pc.instAddr()
+ printMismatchHeader(staticInst, *pc);
+ outs << "diff> [PC] gem5: 0x" << std::hex <<
pc->instAddr()
<< ", TARMAC: 0x" << instRecord.addr << std::endl;
mismatch = true;
mismatchOnPcOrOpcode = true;
@@ -1019,7 +1019,7 @@
if (arm_inst->encoding() != instRecord.opcode) {
if (!mismatch)
- printMismatchHeader(staticInst, pc);
+ printMismatchHeader(staticInst, *pc);
outs << "diff> [opcode] gem5: 0x" << std::hex
<< arm_inst->encoding()
<< ", TARMAC: 0x" << instRecord.opcode <<
std::endl;
@@ -1028,12 +1028,12 @@
}
// Set the Instruction set state.
- isetstate = pcToISetState(pc);
+ isetstate = pcToISetState(*pc);
if (instRecord.isetstate != isetstate &&
isetstate != ISET_UNSUPPORTED) {
if (!mismatch)
- printMismatchHeader(staticInst, pc);
+ printMismatchHeader(staticInst, *pc);
outs << "diff> [iset_state] gem5: "
<< iSetStateToStr(isetstate)
<< ", TARMAC: "
@@ -1054,7 +1054,7 @@
break;
if (written_data != memRecord.data) {
if (!mismatch)
- printMismatchHeader(staticInst, pc);
+ printMismatchHeader(staticInst, *pc);
outs << "diff> [mem(0x" << std::hex << memRecord.addr
<< ")] gem5: 0x" << written_data
<< ", TARMAC: 0x" << memRecord.data
@@ -1073,7 +1073,7 @@
// entries in the TARMAC trace have been parsed
if (destRegRecords.size()) {
TarmacParserRecordEvent *event = new TarmacParserRecordEvent(
- parent, thread, staticInst, pc, mismatch,
+ parent, thread, staticInst, *pc, mismatch,
mismatchOnPcOrOpcode);
mainEventQueue[0]->schedule(event, curTick());
} else if (mismatchOnPcOrOpcode && (parent.exitOnDiff ||
diff --git a/src/arch/arm/tracers/tarmac_parser.hh
b/src/arch/arm/tracers/tarmac_parser.hh
index 6de0172..39cf5c3 100644
--- a/src/arch/arm/tracers/tarmac_parser.hh
+++ b/src/arch/arm/tracers/tarmac_parser.hh
@@ -47,6 +47,7 @@
#define __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
#include <fstream>
+#include <memory>
#include <unordered_map>
#include "base/trace.hh"
@@ -83,7 +84,7 @@
/** Current instruction. */
const StaticInstPtr inst;
/** PC of the current instruction. */
- ArmISA::PCState pc;
+ std::unique_ptr<PCStateBase> pc;
/** True if a mismatch has been detected for this instruction. */
bool mismatch;
/**
@@ -95,10 +96,10 @@
TarmacParserRecordEvent(TarmacParser& _parent,
ThreadContext *_thread,
const StaticInstPtr _inst,
- ArmISA::PCState _pc,
+ const PCStateBase &_pc,
bool _mismatch,
bool _mismatch_on_pc_or_opcode) :
- parent(_parent), thread(_thread), inst(_inst), pc(_pc),
+ parent(_parent), thread(_thread), inst(_inst), pc(_pc.clone()),
mismatch(_mismatch),
mismatchOnPcOrOpcode(_mismatch_on_pc_or_opcode)
{
@@ -130,10 +131,11 @@
* by gem5.
*/
static void printMismatchHeader(const StaticInstPtr inst,
- ArmISA::PCState pc);
+ const PCStateBase &pc);
TarmacParserRecord(Tick _when, ThreadContext *_thread,
- const StaticInstPtr _staticInst, ArmISA::PCState
_pc,
+ const StaticInstPtr _staticInst,
+ const PCStateBase &_pc,
TarmacParser& _parent,
const StaticInstPtr _macroStaticInst = NULL);
@@ -244,17 +246,18 @@
InstRecord *
getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr
staticInst,
- ArmISA::PCState pc,
- const StaticInstPtr macroStaticInst = NULL)
+ const PCStateBase &pc,
+ const StaticInstPtr macroStaticInst=nullptr) override
{
- if (!started && pc.pc() == startPc)
+ if (!started && pc.instAddr() == startPc)
started = true;
- if (started)
+ if (started) {
return new TarmacParserRecord(when, tc, staticInst, pc, *this,
macroStaticInst);
- else
- return NULL;
+ } else {
+ return nullptr;
+ }
}
private:
diff --git a/src/arch/arm/tracers/tarmac_record.cc
b/src/arch/arm/tracers/tarmac_record.cc
index 57d307a..8cd1c81 100644
--- a/src/arch/arm/tracers/tarmac_record.cc
+++ b/src/arch/arm/tracers/tarmac_record.cc
@@ -111,7 +111,7 @@
// TarmacTracerRecord ctor
TarmacTracerRecord::TarmacTracerRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst,
- PCState _pc,
+ const PCStateBase &_pc,
TarmacTracer& _tracer,
const StaticInstPtr _macroStaticInst)
: TarmacBaseRecord(_when, _thread, _staticInst,
@@ -123,7 +123,7 @@
TarmacTracerRecord::TraceInstEntry::TraceInstEntry(
const TarmacContext& tarmCtx,
bool predicate)
- : InstEntry(tarmCtx.thread, tarmCtx.pc, tarmCtx.staticInst,
predicate)
+ : InstEntry(tarmCtx.thread, *tarmCtx.pc, tarmCtx.staticInst,
predicate)
{
secureMode = isSecure(tarmCtx.thread);
@@ -156,7 +156,7 @@
TarmacTracerRecord::TraceRegEntry::TraceRegEntry(
const TarmacContext& tarmCtx,
const RegId& reg)
- : RegEntry(tarmCtx.pc),
+ : RegEntry(*tarmCtx.pc),
regValid(false),
regClass(reg.classValue()),
regRel(reg.index())
@@ -351,7 +351,7 @@
const TarmacContext tarmCtx(
thread,
staticInst->isMicroop()? macroStaticInst : staticInst,
- pc
+ *pc
);
if (!staticInst->isMicroop()) {
diff --git a/src/arch/arm/tracers/tarmac_record.hh
b/src/arch/arm/tracers/tarmac_record.hh
index fb45e9e..197034f 100644
--- a/src/arch/arm/tracers/tarmac_record.hh
+++ b/src/arch/arm/tracers/tarmac_record.hh
@@ -187,7 +187,7 @@
public:
TarmacTracerRecord(Tick _when, ThreadContext *_thread,
- const StaticInstPtr _staticInst, ArmISA::PCState
_pc,
+ const StaticInstPtr _staticInst, const PCStateBase
&_pc,
TarmacTracer& _tracer,
const StaticInstPtr _macroStaticInst = NULL);
diff --git a/src/arch/arm/tracers/tarmac_record_v8.hh
b/src/arch/arm/tracers/tarmac_record_v8.hh
index 4a65806..231945f 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.hh
+++ b/src/arch/arm/tracers/tarmac_record_v8.hh
@@ -147,8 +147,8 @@
public:
TarmacTracerRecordV8(Tick _when, ThreadContext *_thread,
- const StaticInstPtr _staticInst, ArmISA::PCState
_pc,
- TarmacTracer& _parent,
+ const StaticInstPtr _staticInst,
+ const PCStateBase &_pc, TarmacTracer& _parent,
const StaticInstPtr _macroStaticInst = NULL)
: TarmacTracerRecord(_when, _thread, _staticInst, _pc,
_parent, _macroStaticInst)
diff --git a/src/arch/arm/tracers/tarmac_tracer.cc
b/src/arch/arm/tracers/tarmac_tracer.cc
index 06aab74..e017cc4 100644
--- a/src/arch/arm/tracers/tarmac_tracer.cc
+++ b/src/arch/arm/tracers/tarmac_tracer.cc
@@ -76,7 +76,7 @@
InstRecord *
TarmacTracer::getInstRecord(Tick when, ThreadContext *tc,
const StaticInstPtr staticInst,
- ArmISA::PCState pc,
+ const PCStateBase &pc,
const StaticInstPtr macroStaticInst)
{
// Check if we need to start tracing since we have passed the
diff --git a/src/arch/arm/tracers/tarmac_tracer.hh
b/src/arch/arm/tracers/tarmac_tracer.hh
index 908f185..29e82ff 100644
--- a/src/arch/arm/tracers/tarmac_tracer.hh
+++ b/src/arch/arm/tracers/tarmac_tracer.hh
@@ -43,6 +43,8 @@
#ifndef __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__
#define __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__
+#include <memory>
+
#include "arch/arm/tracers/tarmac_record.hh"
#include "arch/arm/tracers/tarmac_record_v8.hh"
#include "params/TarmacTracer.hh"
@@ -64,8 +66,8 @@
public:
TarmacContext(ThreadContext* _thread,
const StaticInstPtr _staticInst,
- ArmISA::PCState _pc)
- : thread(_thread), staticInst(_staticInst), pc(_pc)
+ const PCStateBase &_pc)
+ : thread(_thread), staticInst(_staticInst), pc(_pc.clone())
{}
std::string tarmacCpuName() const;
@@ -73,7 +75,7 @@
public:
ThreadContext* thread;
const StaticInstPtr staticInst;
- ArmISA::PCState pc;
+ std::unique_ptr<PCStateBase> pc;
};
/**
@@ -99,9 +101,8 @@
* - TarmacV8
*/
InstRecord* getInstRecord(Tick when, ThreadContext *tc,
- const StaticInstPtr staticInst,
- ArmISA::PCState pc,
- const StaticInstPtr macroStaticInst = NULL);
+ const StaticInstPtr staticInst, const PCStateBase &pc,
+ const StaticInstPtr macroStaticInst=nullptr) override;
protected:
typedef std::unique_ptr<Printable> PEntryPtr;
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 6c129b9..f6edded 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -76,7 +76,7 @@
if (debug::ExecThread)
outs << "T" << thread->threadId() << " : ";
- Addr cur_pc = pc.instAddr();
+ Addr cur_pc = pc->instAddr();
loader::SymbolTable::const_iterator it;
ccprintf(outs, "%#x", cur_pc);
if (debug::ExecSymbol && (!FullSystem || !in_user_mode) &&
@@ -90,7 +90,7 @@
}
if (inst->isMicroop()) {
- ccprintf(outs, ".%2d", pc.microPC());
+ ccprintf(outs, ".%2d", pc->microPC());
} else {
ccprintf(outs, " ");
}
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index 5dc3ff7..7210241 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -48,7 +48,7 @@
{
public:
ExeTracerRecord(Tick _when, ThreadContext *_thread,
- const StaticInstPtr _staticInst, TheISA::PCState _pc,
+ const StaticInstPtr _staticInst, const PCStateBase &_pc,
const StaticInstPtr _macroStaticInst = NULL)
: InstRecord(_when, _thread, _staticInst, _pc, _macroStaticInst)
{
@@ -68,8 +68,8 @@
InstRecord *
getInstRecord(Tick when, ThreadContext *tc,
- const StaticInstPtr staticInst, TheISA::PCState pc,
- const StaticInstPtr macroStaticInst = NULL)
+ const StaticInstPtr staticInst, const PCStateBase &pc,
+ const StaticInstPtr macroStaticInst=nullptr) override
{
if (!debug::ExecEnable)
return NULL;
diff --git a/src/cpu/inst_pb_trace.cc b/src/cpu/inst_pb_trace.cc
index fbb7470..08a2389 100644
--- a/src/cpu/inst_pb_trace.cc
+++ b/src/cpu/inst_pb_trace.cc
@@ -62,7 +62,7 @@
// instructions that aren't macro-oped
if ((macroStaticInst && staticInst->isFirstMicroop()) ||
!staticInst->isMicroop()) {
- tracer.traceInst(thread, staticInst, pc);
+ tracer.traceInst(thread, staticInst, *pc);
}
// If this instruction accessed memory lets record it
@@ -121,7 +121,7 @@
InstPBTraceRecord*
InstPBTrace::getInstRecord(Tick when, ThreadContext *tc, const
StaticInstPtr si,
- TheISA::PCState pc, const StaticInstPtr mi)
+ const PCStateBase &pc, const StaticInstPtr mi)
{
// Only record the trace if Exec debugging is enabled
if (!debug::ExecEnable)
@@ -132,10 +132,11 @@
}
void
-InstPBTrace::traceInst(ThreadContext *tc, StaticInstPtr si,
TheISA::PCState pc)
+InstPBTrace::traceInst(ThreadContext *tc, StaticInstPtr si,
+ const PCStateBase &pc)
{
if (curMsg) {
- /// @todo if we are running multi-threaded I assume we'd need a
lock here
+ //TODO if we are running multi-threaded I assume we'd need a lock
here
traceStream->write(*curMsg);
delete curMsg;
curMsg = NULL;
@@ -150,7 +151,7 @@
// Create a new instruction message and fill out the fields
curMsg = new ProtoMessage::Inst;
- curMsg->set_pc(pc.pc());
+ curMsg->set_pc(pc.instAddr());
if (instSize == sizeof(uint32_t)) {
curMsg->set_inst(letoh(*reinterpret_cast<uint32_t *>(buf.get())));
} else if (instSize) {
diff --git a/src/cpu/inst_pb_trace.hh b/src/cpu/inst_pb_trace.hh
index 173538a..cfcd47e 100644
--- a/src/cpu/inst_pb_trace.hh
+++ b/src/cpu/inst_pb_trace.hh
@@ -67,7 +67,7 @@
{
public:
InstPBTraceRecord(InstPBTrace& _tracer, Tick when, ThreadContext *tc,
- const StaticInstPtr si, TheISA::PCState pc,
+ const StaticInstPtr si, const PCStateBase &pc,
const StaticInstPtr mi = NULL)
: InstRecord(when, tc, si, pc, mi), tracer(_tracer)
{}
@@ -90,8 +90,8 @@
virtual ~InstPBTrace();
InstPBTraceRecord* getInstRecord(Tick when, ThreadContext *tc, const
- StaticInstPtr si, TheISA::PCState pc,
const
- StaticInstPtr mi = NULL) override;
+ StaticInstPtr si, const PCStateBase
&pc,
+ const StaticInstPtr mi = NULL)
override;
protected:
std::unique_ptr<uint8_t []> buf;
@@ -123,7 +123,7 @@
* @param si for the machInst and opClass
* @param pc for the PC Addr
*/
- void traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState
pc);
+ void traceInst(ThreadContext *tc, StaticInstPtr si, const PCStateBase
&pc);
/** Write a memory request to the trace file as part of the cur
instruction
* @param si for the machInst and opClass
diff --git a/src/cpu/inteltrace.cc b/src/cpu/inteltrace.cc
index 6491ee8..0c3c6c2 100644
--- a/src/cpu/inteltrace.cc
+++ b/src/cpu/inteltrace.cc
@@ -43,7 +43,7 @@
{
std::ostream &outs = Trace::output();
ccprintf(outs, "%7d ) ", when);
- outs << "0x" << std::hex << pc.instAddr() << ":\t";
+ outs << "0x" << std::hex << pc->instAddr() << ":\t";
if (staticInst->isLoad()) {
ccprintf(outs, "<RD %#x>", addr);
} else if (staticInst->isStore()) {
diff --git a/src/cpu/inteltrace.hh b/src/cpu/inteltrace.hh
index 16e0620..4d57026 100644
--- a/src/cpu/inteltrace.hh
+++ b/src/cpu/inteltrace.hh
@@ -46,7 +46,7 @@
{
public:
IntelTraceRecord(Tick _when, ThreadContext *_thread,
- const StaticInstPtr _staticInst, TheISA::PCState _pc,
+ const StaticInstPtr _staticInst, const PCStateBase &_pc,
const StaticInstPtr _macroStaticInst = NULL)
: InstRecord(_when, _thread, _staticInst, _pc,
_macroStaticInst)
@@ -65,7 +65,7 @@
IntelTraceRecord *
getInstRecord(Tick when, ThreadContext *tc,
- const StaticInstPtr staticInst, TheISA::PCState pc,
+ const StaticInstPtr staticInst, const PCStateBase &pc,
const StaticInstPtr macroStaticInst = NULL)
{
if (!debug::ExecEnable)
diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh
index c6730dc..e2756bc 100644
--- a/src/cpu/nativetrace.hh
+++ b/src/cpu/nativetrace.hh
@@ -56,8 +56,8 @@
public:
NativeTraceRecord(NativeTrace * _parent,
Tick _when, ThreadContext *_thread,
- const StaticInstPtr _staticInst, TheISA::PCState _pc,
- const StaticInstPtr _macroStaticInst = NULL)
+ const StaticInstPtr _staticInst, const PCStateBase &_pc,
+ const StaticInstPtr _macroStaticInst=nullptr)
: ExeTracerRecord(_when, _thread, _staticInst, _pc,
_macroStaticInst),
parent(_parent)
{
@@ -80,8 +80,8 @@
NativeTraceRecord *
getInstRecord(Tick when, ThreadContext *tc,
- const StaticInstPtr staticInst, TheISA::PCState pc,
- const StaticInstPtr macroStaticInst = NULL)
+ const StaticInstPtr staticInst, const PCStateBase &pc,
+ const StaticInstPtr macroStaticInst=nullptr) override
{
return new NativeTraceRecord(this, when, tc,
staticInst, pc, macroStaticInst);
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 6c1e3b0..b99af06 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -41,6 +41,9 @@
#ifndef __INSTRECORD_HH__
#define __INSTRECORD_HH__
+#include <memory>
+
+#include "arch/generic/pcstate.hh"
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "base/types.hh"
@@ -66,7 +69,7 @@
// need to make this ref-counted so it doesn't go away before we
// dump the record
StaticInstPtr staticInst;
- TheISA::PCState pc;
+ std::unique_ptr<PCStateBase> pc;
StaticInstPtr macroStaticInst;
// The remaining fields are only valid for particular instruction
@@ -155,14 +158,13 @@
public:
InstRecord(Tick _when, ThreadContext *_thread,
- const StaticInstPtr _staticInst,
- TheISA::PCState _pc,
- const StaticInstPtr _macroStaticInst = NULL)
- : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
- macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
- fetch_seq(0), cp_seq(0), data_status(DataInvalid),
mem_valid(false),
- fetch_seq_valid(false), cp_seq_valid(false), predicate(true),
- faulting(false)
+ const StaticInstPtr _staticInst, const PCStateBase &_pc,
+ const StaticInstPtr _macroStaticInst=nullptr)
+ : when(_when), thread(_thread), staticInst(_staticInst),
+ pc(_pc.clone()), macroStaticInst(_macroStaticInst), addr(0),
size(0),
+ flags(0), fetch_seq(0), cp_seq(0), data_status(DataInvalid),
+ mem_valid(false), fetch_seq_valid(false), cp_seq_valid(false),
+ predicate(true), faulting(false)
{ }
virtual ~InstRecord()
@@ -235,7 +237,7 @@
Tick getWhen() const { return when; }
ThreadContext *getThread() const { return thread; }
StaticInstPtr getStaticInst() const { return staticInst; }
- TheISA::PCState getPCState() const { return pc; }
+ const PCStateBase &getPCState() const { return *pc; }
StaticInstPtr getMacroStaticInst() const { return macroStaticInst; }
Addr getAddr() const { return addr; }
@@ -267,8 +269,8 @@
virtual InstRecord *
getInstRecord(Tick when, ThreadContext *tc,
- const StaticInstPtr staticInst, TheISA::PCState pc,
- const StaticInstPtr macroStaticInst = NULL) = 0;
+ const StaticInstPtr staticInst, const PCStateBase &pc,
+ const StaticInstPtr macroStaticInst=nullptr) = 0;
};
} // namespace Trace
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia31919ef19f973aa7af973889366412f3999342a
Gerrit-Change-Number: 52042
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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